mirror of
https://github.com/pound-emu/ballistic.git
synced 2026-01-31 01:15:21 +01:00
234 lines
10 KiB
XML
234 lines
10 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
|
|
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
|
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
|
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
|
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
|
|
|
<instructionsection id="MOV_INS_advsimd_gen" title="MOV (from general) -- A64" type="alias">
|
|
<docvars>
|
|
<docvar key="alias_mnemonic" value="MOV" />
|
|
<docvar key="instr-class" value="advsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="INS" />
|
|
<docvar key="vector-xfer-type" value="vector-from-general" />
|
|
</docvars>
|
|
<heading>MOV (from general)</heading>
|
|
<desc>
|
|
<brief>
|
|
<para>Move general-purpose register to a vector element</para>
|
|
</brief>
|
|
<authored>
|
|
<para>Move general-purpose register to a vector element. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.</para>
|
|
<para>This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.</para>
|
|
<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
|
|
</authored>
|
|
</desc>
|
|
<operationalnotes>
|
|
<para>If PSTATE.DIT is 1:</para>
|
|
<list type="unordered">
|
|
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
|
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
|
</list>
|
|
</operationalnotes>
|
|
<aliasto refiform="ins_advsimd_gen.xml" iformid="INS_advsimd_gen">INS (general)</aliasto>
|
|
<classes>
|
|
<iclass name="Advanced SIMD" oneof="1" id="iclass_advsimd" no_encodings="1" isa="A64">
|
|
<docvars>
|
|
<docvar key="instr-class" value="advsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="INS" />
|
|
<docvar key="vector-xfer-type" value="vector-from-general" />
|
|
</docvars>
|
|
<iclassintro count="1"></iclassintro>
|
|
<regdiagram form="32" psname="aarch64/instrs/vector/transfer/integer/insert">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" name="op" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="28" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="imm5" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="4" name="imm4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="MOV_INS_asimdins_IR_r" oneofinclass="1" oneof="1" label="">
|
|
<docvars>
|
|
<docvar key="alias_mnemonic" value="MOV" />
|
|
<docvar key="instr-class" value="advsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="INS" />
|
|
<docvar key="vector-xfer-type" value="vector-from-general" />
|
|
</docvars>
|
|
<asmtemplate><text>MOV </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_ts" hover="Element size specifier (field "imm5") [B,D,H,S]"><Ts></a><text>[</text><a link="sa_index" hover="Element index (field "imm5")"><index></a><text>], </text><a link="sa_r" hover="Width specifier for general-purpose source register (field "imm5") [W,X]"><R></a><a link="sa_n" hover="General-purpose source register number [0-30] or ZR (31) (field "Rn")"><n></a></asmtemplate>
|
|
<equivalent_to>
|
|
<asmtemplate><a href="ins_advsimd_gen.xml#INS_asimdins_IR_r">INS</a><text> </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_ts" hover="Element size specifier (field "imm5") [B,D,H,S]"><Ts></a><text>[</text><a link="sa_index" hover="Element index (field "imm5")"><index></a><text>], </text><a link="sa_r" hover="Width specifier for general-purpose source register (field "imm5") [W,X]"><R></a><a link="sa_n" hover="General-purpose source register number [0-30] or ZR (31) (field "Rn")"><n></a></asmtemplate>
|
|
<aliascond>Unconditionally</aliascond>
|
|
</equivalent_to>
|
|
</encoding>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="MOV_INS_asimdins_IR_r" symboldefcount="1">
|
|
<symbol link="sa_vd"><Vd></symbol>
|
|
<account encodedin="Rd">
|
|
<intro>
|
|
<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="MOV_INS_asimdins_IR_r" symboldefcount="1">
|
|
<symbol link="sa_ts"><Ts></symbol>
|
|
<definition encodedin="imm5">
|
|
<intro>Is an element size specifier, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">imm5</entry>
|
|
<entry class="symbol"><Ts></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">x0000</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">xxxx1</entry>
|
|
<entry class="symbol">B</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">xxx10</entry>
|
|
<entry class="symbol">H</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">xx100</entry>
|
|
<entry class="symbol">S</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">x1000</entry>
|
|
<entry class="symbol">D</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="MOV_INS_asimdins_IR_r" symboldefcount="1">
|
|
<symbol link="sa_index"><index></symbol>
|
|
<definition encodedin="imm5">
|
|
<intro>Is the element index </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">imm5</entry>
|
|
<entry class="symbol"><index></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">x0000</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">xxxx1</entry>
|
|
<entry class="symbol">imm5<4:1></entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">xxx10</entry>
|
|
<entry class="symbol">imm5<4:2></entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">xx100</entry>
|
|
<entry class="symbol">imm5<4:3></entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">x1000</entry>
|
|
<entry class="symbol">imm5<4></entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="MOV_INS_asimdins_IR_r" symboldefcount="1">
|
|
<symbol link="sa_r"><R></symbol>
|
|
<definition encodedin="imm5">
|
|
<intro>Is the width specifier for the general-purpose source register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">imm5</entry>
|
|
<entry class="symbol"><R></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">x0000</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">xxxx1</entry>
|
|
<entry class="symbol">W</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">xxx10</entry>
|
|
<entry class="symbol">W</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">xx100</entry>
|
|
<entry class="symbol">W</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">x1000</entry>
|
|
<entry class="symbol">X</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="MOV_INS_asimdins_IR_r" symboldefcount="1">
|
|
<symbol link="sa_n"><n></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the number [0-30] of the general-purpose source register or ZR (31), encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
</instructionsection>
|