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151 lines
8.1 KiB
XML
151 lines
8.1 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="movaz_mz_za2" title="MOVAZ (array to vector, two registers)" type="instruction">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="MOVAZ" />
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</docvars>
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<heading>MOVAZ (array to vector, two registers)</heading>
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<desc>
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<brief>Move and zero two ZA single-vector groups to vector registers</brief>
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<description>
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<para>The instruction operates on two ZA single-vector groups. The ZA single-vector groups are zeroed after moving their contents to the destination vectors. The vector numbers forming the single-vector group within each half of the ZA array are selected by the sum of the vector select register and immediate offset, modulo half the number of ZA array vectors.</para>
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<para>The <arm-defined-word>vector group</arm-defined-word> symbol <syntax>VGx2</syntax> indicates that the instruction operates on two ZA single-vector groups.</para>
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<para>The preferred disassembly syntax uses a 64-bit element size, but an assembler should accept any element size if it is used consistently for all operands. The <arm-defined-word>vector group</arm-defined-word> symbol is preferred for disassembly, but optional in assembler source code.</para>
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<para>This instruction is unpredicated.</para>
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</description>
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<status>Amber</status>
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<predicated>False</predicated>
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<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
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<sm_policy>SM_1_only</sm_policy>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="SME2" oneof="1" id="iclass_mortlach2" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="MOVAZ" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="FEAT_SME2p1" feature="FEAT_SME2p1" />
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</arch_variants>
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<regdiagram form="32" psname="MOVAZ-MZ.ZA2-1">
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<box hibit="31" width="17" settings="17">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="14" width="2" name="Rv" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="12" width="3" settings="3">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="7" width="3" name="off3" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="4" width="4" name="Zd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="0" settings="1">
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<c>0</c>
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</box>
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</regdiagram>
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<encoding name="movaz_mz_za2_1" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="MOVAZ" />
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</docvars>
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<asmtemplate><text>MOVAZ </text><text>{</text><text> </text><a link="sa_zd1" hover="First destination scalable vector register of a multi-vector sequence (field Zd)"><Zd1></a><text>.D-</text><a link="sa_zd2" hover="Second destination scalable vector register of a multi-vector sequence (field Zd)"><Zd2></a><text>.D </text><text>}</text><text>, ZA.D[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offs" hover="Vector select offset [0-7] (field "off3")"><offs></a><a>{, VGx2}</a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="MOVAZ-MZ.ZA2-1" mylink="MOVAZ-MZ.ZA2-1" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2p1.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2p1()">HaveSME2p1</a>() then UNDEFINED;
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integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
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integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off3);
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd:'0');
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constant integer nreg = 2;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="movaz_mz_za2_1" symboldefcount="1">
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<symbol link="sa_zd1"><Zd1></symbol>
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<account encodedin="Zd">
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<intro>
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<para>Is the name of the first destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 2.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="movaz_mz_za2_1" symboldefcount="1">
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<symbol link="sa_zd2"><Zd2></symbol>
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<account encodedin="Zd">
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<intro>
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<para>Is the name of the second destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 2 plus 1.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="movaz_mz_za2_1" symboldefcount="1">
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<symbol link="sa_wv"><Wv></symbol>
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<account encodedin="Rv">
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<intro>
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<para>Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="movaz_mz_za2_1" symboldefcount="1">
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<symbol link="sa_offs"><offs></symbol>
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<account encodedin="off3">
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<intro>
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<para>Is the vector select offset, in the range 0 to 7, encoded in the "off3" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="MOVAZ-MZ.ZA2-1" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEAndZAEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
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constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
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integer vectors = VL DIV 8;
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integer vstride = vectors DIV nreg;
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bits(32) vbase = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[v, 32];
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integer vec = (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vbase) + offset) MOD vstride;
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for r = 0 to nreg-1
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bits(VL) result = <a link="impl-aarch64.ZAvector.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) ZAvector[integer index, integer width]">ZAvector</a>[vec, VL];
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<a link="impl-aarch64.ZAvector.write.2" file="shared_pseudocode.xml" hover="accessor: ZAvector[integer index, integer width] = bits(width) value">ZAvector</a>[vec, VL] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
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<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d + r, VL] = result;
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vec = vec + vstride;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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