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192 lines
9.5 KiB
XML
192 lines
9.5 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="MRRS" title="MRRS -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="system" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="MRRS" />
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</docvars>
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<heading>MRRS</heading>
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<desc>
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<brief>
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<para>Move System Register to two adjacent general-purpose registers</para>
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</brief>
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<authored>
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<para>Move System Register to two adjacent general-purpose registers allows the PE to read an AArch64 128-bit System register into two adjacent 64-bit general-purpose registers.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="System" oneof="1" id="iclass_system" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="system" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="MRRS" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="FEAT_SYSREG128" feature="FEAT_SYSREG128" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/system/register/system_128" tworows="1">
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<box hibit="31" width="10" settings="10">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="21" name="L" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="20" name="op0[1]" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" name="o0" usename="1">
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<c></c>
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</box>
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<box hibit="18" width="3" name="op1" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="15" width="4" name="CRn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" name="CRm" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="7" width="3" name="op2" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="4" width="5" name="Rt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="MRRS_RS_systemmovepr" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="instr-class" value="system" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="MRRS" />
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</docvars>
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<asmtemplate><text>MRRS </text><a link="sa_xt" hover="First 64-bit general-purpose destination register (field "Rt")"><Xt></a><text>, </text><a link="sa_xt_plus_1" hover="Second 64-bit general-purpose destination register, encoded as "Rt" +1 (field Rt)"><Xt+1></a><text>, (</text><a link="sa_systemreg" hover="System register name (field "o0:op1:CRn:CRm:op2")"><systemreg></a><text>|S</text><a link="sa_op0" hover="Unsigned immediate (field "o0") [2,3]"><op0></a><text>_</text><a link="sa_op1" hover="3-bit unsigned immediate [0-7] (field "op1")"><op1></a><text>_</text><a link="sa_cn" hover="Name 'Cn', with 'n' [0-15] (field "CRn")"><Cn></a><text>_</text><a link="sa_cm" hover="Name 'Cm', with 'm' [0-15] (field "CRm")"><Cm></a><text>_</text><a link="sa_op2" hover="3-bit unsigned immediate [0-7] (field "op2")"><op2></a><text>)</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/system/register/system_128" mylink="aarch64.instrs.system.register.system_128" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveSysReg128.0" file="shared_pseudocode.xml" hover="function: boolean HaveSysReg128()">HaveSysReg128</a>() then UNDEFINED;
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if Rt<0> == '1' then UNDEFINED;
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<a link="AArch64.CheckSystemAccess.7" file="shared_pseudocode.xml" hover="function: AArch64.CheckSystemAccess(bits(2) op0, bits(3) op1, bits(4) crn, bits(4) crm, bits(3) op2, bits(5) rt, bit read)">AArch64.CheckSystemAccess</a>('1':o0, op1, CRn, CRm, op2, Rt, L);
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
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integer t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt+1);
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integer sys_op0 = 2 + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(o0);
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integer sys_op1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op1);
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integer sys_op2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op2);
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integer sys_crn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(CRn);
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integer sys_crm = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(CRm);
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boolean read = (L == '1');</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="MRRS_RS_systemmovepr" symboldefcount="1">
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<symbol link="sa_xt"><Xt></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the 64-bit name of the first general-purpose destination register, encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="MRRS_RS_systemmovepr" symboldefcount="1">
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<symbol link="sa_xt_plus_1"><Xt+1></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the 64-bit name of the second general-purpose destination register, encoded as "Rt" +1.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="MRRS_RS_systemmovepr" symboldefcount="1">
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<symbol link="sa_systemreg"><systemreg></symbol>
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<account encodedin="CRm:CRn:o0:op1:op2">
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<intro>
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<para>Is a System register name, encoded in "o0:op1:CRn:CRm:op2".</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="MRRS_RS_systemmovepr" symboldefcount="1">
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<symbol link="sa_op0"><op0></symbol>
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<definition encodedin="o0">
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<intro>Is an unsigned immediate, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">o0</entry>
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<entry class="symbol"><op0></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">2</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">3</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="MRRS_RS_systemmovepr" symboldefcount="1">
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<symbol link="sa_op1"><op1></symbol>
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<account encodedin="op1">
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<intro>
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<para>Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op1" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="MRRS_RS_systemmovepr" symboldefcount="1">
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<symbol link="sa_cn"><Cn></symbol>
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<account encodedin="CRn">
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<intro>
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<para>Is a name 'Cn', with 'n' in the range 0 to 15, encoded in the "CRn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="MRRS_RS_systemmovepr" symboldefcount="1">
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<symbol link="sa_cm"><Cm></symbol>
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<account encodedin="CRm">
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<intro>
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<para>Is a name 'Cm', with 'm' in the range 0 to 15, encoded in the "CRm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="MRRS_RS_systemmovepr" symboldefcount="1">
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<symbol link="sa_op2"><op2></symbol>
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<account encodedin="op2">
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<intro>
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<para>Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/system/register/system_128" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if read then
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<a link="AArch64.SysRegRead128.7" file="shared_pseudocode.xml" hover="function: AArch64.SysRegRead128(integer op0, integer op1, integer crn, integer crm, integer op2, integer t, integer t2)">AArch64.SysRegRead128</a>(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, t, t2);
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else
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<a link="AArch64.SysRegWrite128.7" file="shared_pseudocode.xml" hover="function: AArch64.SysRegWrite128(integer op0, integer op1, integer crn, integer crm, integer op2, integer t, integer t2)">AArch64.SysRegWrite128</a>(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, t, t2);</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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