mirror of
https://github.com/pound-emu/ballistic.git
synced 2026-01-31 01:15:21 +01:00
210 lines
11 KiB
XML
210 lines
11 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
|
|
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
|
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
|
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
|
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
|
|
|
<instructionsection id="NEGS_SUBS_addsub_shift" title="NEGS -- A64" type="alias">
|
|
<docvars>
|
|
<docvar key="alias_mnemonic" value="NEGS" />
|
|
<docvar key="cond-setting" value="S" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="SUBS" />
|
|
</docvars>
|
|
<heading>NEGS</heading>
|
|
<desc>
|
|
<brief>
|
|
<para>Negate, setting flags</para>
|
|
</brief>
|
|
<authored>
|
|
<para>Negate, setting flags, negates an optionally-shifted register value, and writes the result to the destination register. It updates the condition flags based on the result.</para>
|
|
</authored>
|
|
</desc>
|
|
<operationalnotes>
|
|
<para>If PSTATE.DIT is 1:</para>
|
|
<list type="unordered">
|
|
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
|
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
|
</list>
|
|
</operationalnotes>
|
|
<aliasto refiform="subs_addsub_shift.xml" iformid="SUBS_addsub_shift">SUBS (shifted register)</aliasto>
|
|
<classes>
|
|
<iclass name="Setting the condition flags" oneof="1" id="iclass_s" no_encodings="2" isa="A64">
|
|
<docvars>
|
|
<docvar key="cond-setting" value="S" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="SUBS" />
|
|
</docvars>
|
|
<iclassintro count="2"></iclassintro>
|
|
<regdiagram form="32" psname="aarch64/instrs/integer/arithmetic/add-sub/shiftedreg" tworows="1">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" name="op" usename="1" settings="1" psbits="x">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1" settings="1" psbits="x">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="shift" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" name="imm6" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1" settings="5" psbits="xxxxx">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1" settings="5" constraint="!= 11111" psbits="xxxxx">
|
|
<c colspan="5">!= 11111</c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="NEGS_SUBS_32_addsub_shift" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
|
|
<docvars>
|
|
<docvar key="alias_mnemonic" value="NEGS" />
|
|
<docvar key="cond-setting" value="S" />
|
|
<docvar key="datatype" value="32" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="SUBS" />
|
|
</docvars>
|
|
<box hibit="31" width="1" name="sf">
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>NEGS </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_wm_1" hover="32-bit general-purpose source register (field "Rm")"><Wm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional shift type applied to second source operand, default LSL (field "shift") [ASR,LSL,LSR]"><shift></a><text> #</text><a link="sa_amount" hover="Shift amount [0-31], default 0 (field "imm6")"><amount></a><text>}</text></asmtemplate>
|
|
<equivalent_to>
|
|
<asmtemplate><a href="subs_addsub_shift.xml#SUBS_32_addsub_shift">SUBS</a><text> </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, WZR, </text><a link="sa_wm_1" hover="32-bit general-purpose source register (field "Rm")"><Wm></a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Optional shift type applied to second source operand, default LSL (field "shift") [ASR,LSL,LSR]"><shift></a><text> #</text><a link="sa_amount" hover="Shift amount [0-31], default 0 (field "imm6")"><amount></a><text>}</text></asmtemplate>
|
|
<aliascond>Unconditionally</aliascond>
|
|
</equivalent_to>
|
|
</encoding>
|
|
<encoding name="NEGS_SUBS_64_addsub_shift" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
|
|
<docvars>
|
|
<docvar key="alias_mnemonic" value="NEGS" />
|
|
<docvar key="cond-setting" value="S" />
|
|
<docvar key="datatype" value="64" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="SUBS" />
|
|
</docvars>
|
|
<box hibit="31" width="1" name="sf">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>NEGS </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xm_1" hover="64-bit general-purpose source register (field "Rm")"><Xm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional shift type applied to second source operand, default LSL (field "shift") [ASR,LSL,LSR]"><shift></a><text> #</text><a link="sa_amount_1" hover="Shift amount [0-63], default 0 (field "imm6")"><amount></a><text>}</text></asmtemplate>
|
|
<equivalent_to>
|
|
<asmtemplate><a href="subs_addsub_shift.xml#SUBS_64_addsub_shift">SUBS</a><text> </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, XZR, </text><a link="sa_xm_1" hover="64-bit general-purpose source register (field "Rm")"><Xm></a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Optional shift type applied to second source operand, default LSL (field "shift") [ASR,LSL,LSR]"><shift></a><text> #</text><a link="sa_amount_1" hover="Shift amount [0-63], default 0 (field "imm6")"><amount></a><text>}</text></asmtemplate>
|
|
<aliascond>Unconditionally</aliascond>
|
|
</equivalent_to>
|
|
</encoding>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="NEGS_SUBS_32_addsub_shift" symboldefcount="1">
|
|
<symbol link="sa_wd"><Wd></symbol>
|
|
<account encodedin="Rd">
|
|
<intro>
|
|
<para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="NEGS_SUBS_32_addsub_shift" symboldefcount="1">
|
|
<symbol link="sa_wm_1"><Wm></symbol>
|
|
<account encodedin="Rm">
|
|
<intro>
|
|
<para>Is the 32-bit name of the general-purpose source register, encoded in the "Rm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="NEGS_SUBS_64_addsub_shift" symboldefcount="1">
|
|
<symbol link="sa_xd"><Xd></symbol>
|
|
<account encodedin="Rd">
|
|
<intro>
|
|
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="NEGS_SUBS_64_addsub_shift" symboldefcount="1">
|
|
<symbol link="sa_xm_1"><Xm></symbol>
|
|
<account encodedin="Rm">
|
|
<intro>
|
|
<para>Is the 64-bit name of the general-purpose source register, encoded in the "Rm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="NEGS_SUBS_32_addsub_shift, NEGS_SUBS_64_addsub_shift" symboldefcount="1">
|
|
<symbol link="sa_shift"><shift></symbol>
|
|
<definition encodedin="shift">
|
|
<intro>Is the optional shift type to be applied to the second source operand, defaulting to LSL and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">shift</entry>
|
|
<entry class="symbol"><shift></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">LSL</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">LSR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">ASR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="NEGS_SUBS_32_addsub_shift" symboldefcount="1">
|
|
<symbol link="sa_amount"><amount></symbol>
|
|
<account encodedin="imm6">
|
|
<docvars>
|
|
<docvar key="datatype" value="32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For the 32-bit variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="NEGS_SUBS_64_addsub_shift" symboldefcount="2">
|
|
<symbol link="sa_amount_1"><amount></symbol>
|
|
<account encodedin="imm6">
|
|
<docvars>
|
|
<docvar key="datatype" value="64" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For the 64-bit variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
</instructionsection>
|