mirror of
https://github.com/pound-emu/ballistic.git
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324 lines
17 KiB
XML
324 lines
17 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="ORR_advsimd_imm" title="ORR (vector, immediate) -- A64" type="instruction">
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<docvars>
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<docvar key="asimdimm-immtype" value="shifted-immediate" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ORR" />
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</docvars>
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<heading>ORR (vector, immediate)</heading>
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<desc>
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<brief>
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<para>Bitwise inclusive OR (vector, immediate)</para>
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</brief>
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<authored>
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<para>Bitwise inclusive OR (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise OR between each result and an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.</para>
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<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
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</authored>
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</desc>
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<operationalnotes>
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<para>If PSTATE.DIT is 1:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Shifted immediate" oneof="1" id="iclass_shifted_immediate" no_encodings="2" isa="A64">
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<docvars>
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<docvar key="asimdimm-immtype" value="shifted-immediate" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ORR" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/vector/logical" tworows="1">
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<box hibit="31" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="29" name="op" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="28" width="10" settings="10">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="18" name="a" usename="1">
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<c></c>
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</box>
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<box hibit="17" name="b" usename="1">
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<c></c>
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</box>
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<box hibit="16" name="c" usename="1">
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<c></c>
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</box>
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<box hibit="15" width="4" name="cmode" usename="1" settings="1" psbits="xxxx">
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<c>x</c>
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<c>x</c>
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<c>x</c>
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<c>1</c>
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</box>
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<box hibit="11" name="o2" settings="1">
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<c>0</c>
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</box>
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<box hibit="10" settings="1">
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<c>1</c>
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</box>
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<box hibit="9" name="d" usename="1">
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<c></c>
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</box>
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<box hibit="8" name="e" usename="1">
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<c></c>
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</box>
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<box hibit="7" name="f" usename="1">
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<c></c>
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</box>
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<box hibit="6" name="g" usename="1">
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<c></c>
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</box>
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<box hibit="5" name="h" usename="1">
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<c></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="ORR_asimdimm_L_hl" oneofinclass="2" oneof="2" label="16-bit" bitdiffs="cmode == 10x1">
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<docvars>
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<docvar key="asimdimm-datatype" value="per-halfword" />
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<docvar key="asimdimm-immtype" value="shifted-immediate" />
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<docvar key="asimdimm-type" value="per-halfword-shifted-immediate" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ORR" />
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</docvars>
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<box hibit="15" width="4" name="cmode">
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<c>1</c>
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<c>0</c>
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<c></c>
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<c></c>
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</box>
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<asmtemplate><text>ORR </text><a link="sa_vd" hover="SIMD&FP register (field "Rd")"><Vd></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "Q") [4H,8H]"><T></a><text>, #</text><a link="sa_imm8" hover="8-bit immediate (field "a:b:c:d:e:f:g:h")"><imm8></a><text>{</text><text>, LSL #</text><a link="sa_amount" hover="Shift amount (field "cmode<1>") [0,8]"><amount></a><text>}</text></asmtemplate>
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</encoding>
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<encoding name="ORR_asimdimm_L_sl" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="cmode == 0xx1">
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<docvars>
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<docvar key="asimdimm-datatype" value="per-word" />
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<docvar key="asimdimm-immtype" value="shifted-immediate" />
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<docvar key="asimdimm-type" value="per-word-shifted-immediate" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ORR" />
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</docvars>
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<box hibit="15" width="4" name="cmode">
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<c>0</c>
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<c></c>
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<c></c>
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<c></c>
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</box>
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<asmtemplate><text>ORR </text><a link="sa_vd" hover="SIMD&FP register (field "Rd")"><Vd></a><text>.</text><a link="sa_t_1" hover="Arrangement specifier (field "Q") [2S,4S]"><T></a><text>, #</text><a link="sa_imm8" hover="8-bit immediate (field "a:b:c:d:e:f:g:h")"><imm8></a><text>{</text><text>, LSL #</text><a link="sa_amount_1" hover="Shift amount (field "cmode<2:1>") [0,8,16,24]"><amount></a><text>}</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/logical" mylink="aarch64.instrs.vector.logical" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer rd = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer datasize = if Q == '1' then 128 else 64;
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bits(datasize) imm;
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bits(64) imm64;
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<a link="ImmediateOp" file="shared_pseudocode.xml" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp</a> operation;
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case cmode:op of
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when '0xx00' operation = <a link="ImmediateOp_MOVI" file="shared_pseudocode.xml" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp_MOVI</a>;
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when '0xx01' operation = <a link="ImmediateOp_MVNI" file="shared_pseudocode.xml" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp_MVNI</a>;
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when '0xx10' operation = <a link="ImmediateOp_ORR" file="shared_pseudocode.xml" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp_ORR</a>;
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when '0xx11' operation = <a link="ImmediateOp_BIC" file="shared_pseudocode.xml" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp_BIC</a>;
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when '10x00' operation = <a link="ImmediateOp_MOVI" file="shared_pseudocode.xml" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp_MOVI</a>;
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when '10x01' operation = <a link="ImmediateOp_MVNI" file="shared_pseudocode.xml" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp_MVNI</a>;
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when '10x10' operation = <a link="ImmediateOp_ORR" file="shared_pseudocode.xml" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp_ORR</a>;
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when '10x11' operation = <a link="ImmediateOp_BIC" file="shared_pseudocode.xml" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp_BIC</a>;
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when '110x0' operation = <a link="ImmediateOp_MOVI" file="shared_pseudocode.xml" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp_MOVI</a>;
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when '110x1' operation = <a link="ImmediateOp_MVNI" file="shared_pseudocode.xml" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp_MVNI</a>;
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when '1110x' operation = <a link="ImmediateOp_MOVI" file="shared_pseudocode.xml" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp_MOVI</a>;
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when '11110' operation = <a link="ImmediateOp_MOVI" file="shared_pseudocode.xml" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp_MOVI</a>;
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when '11111'
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// FMOV Dn,#imm is in main FP instruction set
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if Q == '0' then UNDEFINED;
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operation = <a link="ImmediateOp_MOVI" file="shared_pseudocode.xml" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp_MOVI</a>;
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imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>(op, cmode, a:b:c:d:e:f:g:h);
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imm = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(imm64, datasize DIV 64);</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="ORR_asimdimm_L_hl, ORR_asimdimm_L_sl" symboldefcount="1">
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<symbol link="sa_vd"><Vd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the name of the SIMD&FP register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ORR_asimdimm_L_hl" symboldefcount="1">
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<symbol link="sa_t"><T></symbol>
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<definition encodedin="Q">
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<intro>For the 16-bit variant: is an arrangement specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">Q</entry>
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<entry class="symbol"><T></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">4H</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">8H</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="ORR_asimdimm_L_sl" symboldefcount="2">
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<symbol link="sa_t_1"><T></symbol>
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<definition encodedin="Q">
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<intro>For the 32-bit variant: is an arrangement specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">Q</entry>
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<entry class="symbol"><T></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">2S</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">4S</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="ORR_asimdimm_L_hl, ORR_asimdimm_L_sl" symboldefcount="1">
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<symbol link="sa_imm8"><imm8></symbol>
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<account encodedin="a:b:c:d:e:f:g:h">
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<intro>
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<para>Is an 8-bit immediate encoded in "a:b:c:d:e:f:g:h".</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ORR_asimdimm_L_hl" symboldefcount="1">
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<symbol link="sa_amount"><amount></symbol>
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<definition encodedin="cmode<1>">
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<intro>For the 16-bit variant: is the shift amount </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">cmode<1></entry>
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<entry class="symbol"><amount></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">0</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">8</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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<after> defaulting to 0 if LSL is omitted.</after>
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</definition>
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</explanation>
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<explanation enclist="ORR_asimdimm_L_sl" symboldefcount="2">
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<symbol link="sa_amount_1"><amount></symbol>
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<definition encodedin="cmode<2:1>">
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<intro>For the 32-bit variant: is the shift amount </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">cmode<2:1></entry>
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<entry class="symbol"><amount></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="symbol">0</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="symbol">8</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="symbol">16</entry>
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</row>
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<row>
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<entry class="bitfield">11</entry>
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<entry class="symbol">24</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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<after> defaulting to 0 if LSL is omitted.</after>
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</definition>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/logical" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
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bits(datasize) operand;
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bits(datasize) result;
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case operation of
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when <a link="ImmediateOp_MOVI" file="shared_pseudocode.xml" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp_MOVI</a>
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result = imm;
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when <a link="ImmediateOp_MVNI" file="shared_pseudocode.xml" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp_MVNI</a>
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result = NOT(imm);
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when <a link="ImmediateOp_ORR" file="shared_pseudocode.xml" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp_ORR</a>
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operand = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[rd, datasize];
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result = operand OR imm;
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when <a link="ImmediateOp_BIC" file="shared_pseudocode.xml" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp_BIC</a>
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operand = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[rd, datasize];
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result = operand AND NOT(imm);
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<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[rd, datasize] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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