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archived-ballistic/spec/arm64_xml/prfd_i_p_ai.xml
Ronald Caesar 26a677f8b4 decoder: Add ARM specification docs
Signed-off-by: Ronald Caesar <github43132@proton.me>
2025-12-12 18:11:36 -04:00

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<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<instructionsection id="prfd_i_p_ai" title="PRFD (vector plus immediate)" type="instruction">
<docvars>
<docvar key="instr-class" value="sve" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="PRFD" />
<docvar key="sve-esize" value="esize-doubleword" />
</docvars>
<heading>PRFD (vector plus immediate)</heading>
<desc>
<brief>Gather prefetch doublewords (vector plus immediate)</brief>
<description>
<para>Gather prefetch of doublewords from the active memory addresses generated by a vector base plus immediate index. The index is a multiple of 8 in the range 0 to 248. Inactive addresses are not prefetched from memory.</para>
<para>The <syntax>&lt;prfop&gt;</syntax> symbol specifies the prefetch hint as a combination of three options: access type <value>PLD</value> for load or <value>PST</value> for store; target cache level <value>L1</value>, <value>L2</value> or <value>L3</value>; temporality (<value>KEEP</value> for temporal or <value>STRM</value> for non-temporal).</para>
<para>This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.</para>
</description>
<status>Green</status>
<predicated>True</predicated>
<sm_policy>SM_0_only</sm_policy>
</desc>
<alias_list howmany="0"></alias_list>
<classes>
<classesintro count="2">
<txt>It has encodings from 2 classes:</txt>
<a href="#iclass_32_elem">32-bit element</a>
<txt> and </txt>
<a href="#iclass_64_elem">64-bit element</a>
</classesintro>
<iclass name="32-bit element" oneof="2" id="iclass_32_elem" no_encodings="1" isa="A64">
<docvars>
<docvar key="instr-class" value="sve" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="PRFD" />
<docvar key="sve-elem-type" value="32-elem" />
<docvar key="sve-esize" value="esize-doubleword" />
</docvars>
<iclassintro count="1"></iclassintro>
<regdiagram form="32" psname="PRFD-I.P.AI-S" tworows="1">
<box hibit="31" width="7" settings="7">
<c>1</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>1</c>
<c>0</c>
</box>
<box hibit="24" name="msz&lt;1&gt;" usename="1" settings="1">
<c>1</c>
</box>
<box hibit="23" name="msz&lt;0&gt;" usename="1" settings="1">
<c>1</c>
</box>
<box hibit="22" width="2" settings="2">
<c>0</c>
<c>0</c>
</box>
<box hibit="20" width="5" name="imm5" usename="1">
<c colspan="5"></c>
</box>
<box hibit="15" width="3" settings="3">
<c>1</c>
<c>1</c>
<c>1</c>
</box>
<box hibit="12" width="3" name="Pg" usename="1">
<c colspan="3"></c>
</box>
<box hibit="9" width="5" name="Zn" usename="1">
<c colspan="5"></c>
</box>
<box hibit="4" settings="1">
<c>0</c>
</box>
<box hibit="3" width="4" name="prfop" usename="1">
<c colspan="4"></c>
</box>
</regdiagram>
<encoding name="prfd_i_p_ai_s" oneofinclass="1" oneof="2" label="">
<docvars>
<docvar key="instr-class" value="sve" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="PRFD" />
<docvar key="sve-elem-type" value="32-elem" />
<docvar key="sve-esize" value="esize-doubleword" />
</docvars>
<asmtemplate><text>PRFD </text><a link="sa_prfop" hover="Prefetch operation specifier (field &quot;prfop&quot;) [#uimm4,PLDL1KEEP,PLDL1STRM,PLDL2KEEP,PLDL2STRM,PLDL3KEEP,PLDL3STRM,PSTL1KEEP,PSTL1STRM,PSTL2KEEP,PSTL2STRM,PSTL3KEEP,PSTL3STRM]">&lt;prfop&gt;</a><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field &quot;Pg&quot;)">&lt;Pg&gt;</a><text>, [</text><a link="sa_zn" hover="Base scalable vector register (field &quot;Zn&quot;)">&lt;Zn&gt;</a><text>.S</text><text>{</text><text>, #</text><a link="sa_imm" hover="Optional unsigned immediate byte offset, multiple of 8 [0-248], default 0 (field &quot;imm5&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
</encoding>
<ps_section howmany="1">
<ps name="PRFD-I.P.AI-S" mylink="PRFD-I.P.AI-S" enclabels="" sections="1" secttype="noheading">
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
constant integer esize = 32;
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer level = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(prfop&lt;2:1&gt;);
boolean stream = (prfop&lt;0&gt; == '1');
pref_hint = if prfop&lt;3&gt; == '0' then <a link="Prefetch_READ" file="shared_pseudocode.xml" hover="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">Prefetch_READ</a> else <a link="Prefetch_WRITE" file="shared_pseudocode.xml" hover="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">Prefetch_WRITE</a>;
integer scale = 3;
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm5);</pstext>
</ps>
</ps_section>
</iclass>
<iclass name="64-bit element" oneof="2" id="iclass_64_elem" no_encodings="1" isa="A64">
<docvars>
<docvar key="instr-class" value="sve" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="PRFD" />
<docvar key="sve-elem-type" value="64-elem" />
<docvar key="sve-esize" value="esize-doubleword" />
</docvars>
<iclassintro count="1"></iclassintro>
<regdiagram form="32" psname="PRFD-I.P.AI-D" tworows="1">
<box hibit="31" width="7" settings="7">
<c>1</c>
<c>1</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>1</c>
<c>0</c>
</box>
<box hibit="24" name="msz&lt;1&gt;" usename="1" settings="1">
<c>1</c>
</box>
<box hibit="23" name="msz&lt;0&gt;" usename="1" settings="1">
<c>1</c>
</box>
<box hibit="22" width="2" settings="2">
<c>0</c>
<c>0</c>
</box>
<box hibit="20" width="5" name="imm5" usename="1">
<c colspan="5"></c>
</box>
<box hibit="15" width="3" settings="3">
<c>1</c>
<c>1</c>
<c>1</c>
</box>
<box hibit="12" width="3" name="Pg" usename="1">
<c colspan="3"></c>
</box>
<box hibit="9" width="5" name="Zn" usename="1">
<c colspan="5"></c>
</box>
<box hibit="4" settings="1">
<c>0</c>
</box>
<box hibit="3" width="4" name="prfop" usename="1">
<c colspan="4"></c>
</box>
</regdiagram>
<encoding name="prfd_i_p_ai_d" oneofinclass="1" oneof="2" label="">
<docvars>
<docvar key="instr-class" value="sve" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="PRFD" />
<docvar key="sve-elem-type" value="64-elem" />
<docvar key="sve-esize" value="esize-doubleword" />
</docvars>
<asmtemplate><text>PRFD </text><a link="sa_prfop" hover="Prefetch operation specifier (field &quot;prfop&quot;) [#uimm4,PLDL1KEEP,PLDL1STRM,PLDL2KEEP,PLDL2STRM,PLDL3KEEP,PLDL3STRM,PSTL1KEEP,PSTL1STRM,PSTL2KEEP,PSTL2STRM,PSTL3KEEP,PSTL3STRM]">&lt;prfop&gt;</a><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field &quot;Pg&quot;)">&lt;Pg&gt;</a><text>, [</text><a link="sa_zn" hover="Base scalable vector register (field &quot;Zn&quot;)">&lt;Zn&gt;</a><text>.D</text><text>{</text><text>, #</text><a link="sa_imm" hover="Optional unsigned immediate byte offset, multiple of 8 [0-248], default 0 (field &quot;imm5&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
</encoding>
<ps_section howmany="1">
<ps name="PRFD-I.P.AI-D" mylink="PRFD-I.P.AI-D" enclabels="" sections="1" secttype="noheading">
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
constant integer esize = 64;
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer level = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(prfop&lt;2:1&gt;);
boolean stream = (prfop&lt;0&gt; == '1');
pref_hint = if prfop&lt;3&gt; == '0' then <a link="Prefetch_READ" file="shared_pseudocode.xml" hover="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">Prefetch_READ</a> else <a link="Prefetch_WRITE" file="shared_pseudocode.xml" hover="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">Prefetch_WRITE</a>;
integer scale = 3;
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm5);</pstext>
</ps>
</ps_section>
</iclass>
</classes>
<explanations scope="all">
<explanation enclist="prfd_i_p_ai_d, prfd_i_p_ai_s" symboldefcount="1">
<symbol link="sa_prfop">&lt;prfop&gt;</symbol>
<definition encodedin="prfop">
<intro>Is the prefetch operation specifier, </intro>
<table class="valuetable">
<tgroup cols="2">
<thead>
<row>
<entry class="bitfield">prfop</entry>
<entry class="symbol">&lt;prfop&gt;</entry>
</row>
</thead>
<tbody>
<row>
<entry class="bitfield">0000</entry>
<entry class="symbol">PLDL1KEEP</entry>
</row>
<row>
<entry class="bitfield">0001</entry>
<entry class="symbol">PLDL1STRM</entry>
</row>
<row>
<entry class="bitfield">0010</entry>
<entry class="symbol">PLDL2KEEP</entry>
</row>
<row>
<entry class="bitfield">0011</entry>
<entry class="symbol">PLDL2STRM</entry>
</row>
<row>
<entry class="bitfield">0100</entry>
<entry class="symbol">PLDL3KEEP</entry>
</row>
<row>
<entry class="bitfield">0101</entry>
<entry class="symbol">PLDL3STRM</entry>
</row>
<row>
<entry class="bitfield">x11x</entry>
<entry class="symbol">#uimm4</entry>
</row>
<row>
<entry class="bitfield">1000</entry>
<entry class="symbol">PSTL1KEEP</entry>
</row>
<row>
<entry class="bitfield">1001</entry>
<entry class="symbol">PSTL1STRM</entry>
</row>
<row>
<entry class="bitfield">1010</entry>
<entry class="symbol">PSTL2KEEP</entry>
</row>
<row>
<entry class="bitfield">1011</entry>
<entry class="symbol">PSTL2STRM</entry>
</row>
<row>
<entry class="bitfield">1100</entry>
<entry class="symbol">PSTL3KEEP</entry>
</row>
<row>
<entry class="bitfield">1101</entry>
<entry class="symbol">PSTL3STRM</entry>
</row>
</tbody>
</tgroup>
</table>
</definition>
</explanation>
<explanation enclist="prfd_i_p_ai_d, prfd_i_p_ai_s" symboldefcount="1">
<symbol link="sa_pg">&lt;Pg&gt;</symbol>
<account encodedin="Pg">
<intro>
<para>Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="prfd_i_p_ai_d, prfd_i_p_ai_s" symboldefcount="1">
<symbol link="sa_zn">&lt;Zn&gt;</symbol>
<account encodedin="Zn">
<intro>
<para>Is the name of the base scalable vector register, encoded in the "Zn" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="prfd_i_p_ai_d, prfd_i_p_ai_s" symboldefcount="1">
<symbol link="sa_imm">&lt;imm&gt;</symbol>
<account encodedin="imm5">
<intro>
<para>Is the optional unsigned immediate byte offset, a multiple of 8 in the range 0 to 248, defaulting to 0, encoded in the "imm5" field.</para>
</intro>
</account>
</explanation>
</explanations>
<ps_section howmany="1">
<ps name="PRFD-I.P.AI-S" mylink="execute" enclabels="" sections="1" secttype="Operation">
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckNonStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
bits(VL) base;
if <a link="impl-aarch64.AnyActiveElement.2" file="shared_pseudocode.xml" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then
base = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
for e = 0 to elements-1
if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
bits(64) addr = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[base, e, esize], 64) + (offset &lt;&lt; scale);
<a link="impl-shared.Hint_Prefetch.4" file="shared_pseudocode.xml" hover="function: Hint_Prefetch(bits(64) address, PrefetchHint hint, integer target, boolean stream)">Hint_Prefetch</a>(addr, pref_hint, level, stream);</pstext>
</ps>
</ps_section>
</instructionsection>