mirror of
https://github.com/pound-emu/ballistic.git
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411 lines
22 KiB
XML
411 lines
22 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="prfh_i_p_bz" title="PRFH (scalar plus vector)" type="instruction">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="PRFH" />
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<docvar key="sve-esize" value="esize-halfword" />
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</docvars>
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<heading>PRFH (scalar plus vector)</heading>
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<desc>
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<brief>Gather prefetch halfwords (scalar plus vector)</brief>
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<description>
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<para>Gather prefetch of halfwords from the active memory addresses generated by a 64-bit scalar base plus vector index. The index values are optionally first sign or zero-extended from 32 to 64 bits and then multiplied by 2. Inactive addresses are not prefetched from memory.</para>
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<para>The <syntax><prfop></syntax> symbol specifies the prefetch hint as a combination of three options: access type <value>PLD</value> for load or <value>PST</value> for store; target cache level <value>L1</value>, <value>L2</value> or <value>L3</value>; temporality (<value>KEEP</value> for temporal or <value>STRM</value> for non-temporal).</para>
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<para>This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.</para>
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</description>
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<status>Green</status>
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<predicated>True</predicated>
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<sm_policy>SM_0_only</sm_policy>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="3">
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<txt>It has encodings from 3 classes:</txt>
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<a href="#iclass_off_s_x32_scaled">32-bit scaled offset</a>
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<txt>, </txt>
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<a href="#iclass_off_d_x32_scaled">32-bit unpacked scaled offset</a>
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<txt> and </txt>
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<a href="#iclass_off_d_64_scaled">64-bit scaled offset</a>
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</classesintro>
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<iclass name="32-bit scaled offset" oneof="3" id="iclass_off_s_x32_scaled" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="PRFH" />
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<docvar key="sve-esize" value="esize-halfword" />
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<docvar key="sve-offset-type" value="off_s_x32_scaled" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="PRFH-I.P.BZ-S.x32.scaled" tworows="1">
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<box hibit="31" width="9" settings="9">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="22" name="xs" usename="1">
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<c></c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Zm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" settings="1">
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<c>0</c>
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</box>
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<box hibit="14" name="msz<1>" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="13" name="msz<0>" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="12" width="3" name="Pg" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="prfop" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="prfh_i_p_bz_s_x32_scaled" oneofinclass="1" oneof="3" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="PRFH" />
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<docvar key="sve-esize" value="esize-halfword" />
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<docvar key="sve-offset-type" value="off_s_x32_scaled" />
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</docvars>
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<asmtemplate><text>PRFH </text><a link="sa_prfop" hover="Prefetch operation specifier (field "prfop") [#uimm4,PLDL1KEEP,PLDL1STRM,PLDL2KEEP,PLDL2STRM,PLDL3KEEP,PLDL3STRM,PSTL1KEEP,PSTL1STRM,PSTL2KEEP,PSTL2STRM,PSTL3KEEP,PSTL3STRM]"><prfop></a><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>, </text><a link="sa_zm" hover="Offset scalable vector register (field "Zm")"><Zm></a><text>.S, </text><a link="sa_mod" hover="Index extend and shift specifier (field "xs") [SXTW,UXTW]"><mod></a><text> #1]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="PRFH-I.P.BZ-S.x32.scaled" mylink="PRFH-I.P.BZ-S.x32.scaled" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
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constant integer esize = 32;
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integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
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integer level = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(prfop<2:1>);
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boolean stream = (prfop<0> == '1');
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pref_hint = if prfop<3> == '0' then <a link="Prefetch_READ" file="shared_pseudocode.xml" hover="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">Prefetch_READ</a> else <a link="Prefetch_WRITE" file="shared_pseudocode.xml" hover="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">Prefetch_WRITE</a>;
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constant integer offs_size = 32;
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boolean offs_unsigned = (xs == '0');
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integer scale = 1;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="32-bit unpacked scaled offset" oneof="3" id="iclass_off_d_x32_scaled" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="PRFH" />
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<docvar key="sve-esize" value="esize-halfword" />
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<docvar key="sve-offset-type" value="off_d_x32_scaled" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="PRFH-I.P.BZ-D.x32.scaled" tworows="1">
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<box hibit="31" width="9" settings="9">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="22" name="xs" usename="1">
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<c></c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Zm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" settings="1">
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<c>0</c>
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</box>
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<box hibit="14" name="msz<1>" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="13" name="msz<0>" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="12" width="3" name="Pg" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="prfop" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="prfh_i_p_bz_d_x32_scaled" oneofinclass="1" oneof="3" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="PRFH" />
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<docvar key="sve-esize" value="esize-halfword" />
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<docvar key="sve-offset-type" value="off_d_x32_scaled" />
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</docvars>
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<asmtemplate><text>PRFH </text><a link="sa_prfop" hover="Prefetch operation specifier (field "prfop") [#uimm4,PLDL1KEEP,PLDL1STRM,PLDL2KEEP,PLDL2STRM,PLDL3KEEP,PLDL3STRM,PSTL1KEEP,PSTL1STRM,PSTL2KEEP,PSTL2STRM,PSTL3KEEP,PSTL3STRM]"><prfop></a><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>, </text><a link="sa_zm" hover="Offset scalable vector register (field "Zm")"><Zm></a><text>.D, </text><a link="sa_mod" hover="Index extend and shift specifier (field "xs") [SXTW,UXTW]"><mod></a><text> #1]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="PRFH-I.P.BZ-D.x32.scaled" mylink="PRFH-I.P.BZ-D.x32.scaled" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
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constant integer esize = 64;
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integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
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integer level = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(prfop<2:1>);
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boolean stream = (prfop<0> == '1');
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pref_hint = if prfop<3> == '0' then <a link="Prefetch_READ" file="shared_pseudocode.xml" hover="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">Prefetch_READ</a> else <a link="Prefetch_WRITE" file="shared_pseudocode.xml" hover="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">Prefetch_WRITE</a>;
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constant integer offs_size = 32;
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boolean offs_unsigned = (xs == '0');
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integer scale = 1;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="64-bit scaled offset" oneof="3" id="iclass_off_d_64_scaled" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="PRFH" />
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<docvar key="sve-esize" value="esize-halfword" />
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<docvar key="sve-offset-type" value="off_d_64_scaled" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="PRFH-I.P.BZ-D.64.scaled" tworows="1">
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<box hibit="31" width="11" settings="11">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Zm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" settings="1">
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<c>1</c>
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</box>
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<box hibit="14" name="msz<1>" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="13" name="msz<0>" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="12" width="3" name="Pg" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="prfop" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="prfh_i_p_bz_d_64_scaled" oneofinclass="1" oneof="3" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="PRFH" />
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<docvar key="sve-esize" value="esize-halfword" />
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<docvar key="sve-offset-type" value="off_d_64_scaled" />
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</docvars>
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<asmtemplate><text>PRFH </text><a link="sa_prfop" hover="Prefetch operation specifier (field "prfop") [#uimm4,PLDL1KEEP,PLDL1STRM,PLDL2KEEP,PLDL2STRM,PLDL3KEEP,PLDL3STRM,PSTL1KEEP,PSTL1STRM,PSTL2KEEP,PSTL2STRM,PSTL3KEEP,PSTL3STRM]"><prfop></a><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>, </text><a link="sa_zm" hover="Offset scalable vector register (field "Zm")"><Zm></a><text>.D, LSL #1]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="PRFH-I.P.BZ-D.64.scaled" mylink="PRFH-I.P.BZ-D.64.scaled" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
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constant integer esize = 64;
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integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
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integer level = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(prfop<2:1>);
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boolean stream = (prfop<0> == '1');
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pref_hint = if prfop<3> == '0' then <a link="Prefetch_READ" file="shared_pseudocode.xml" hover="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">Prefetch_READ</a> else <a link="Prefetch_WRITE" file="shared_pseudocode.xml" hover="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">Prefetch_WRITE</a>;
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constant integer offs_size = 64;
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boolean offs_unsigned = TRUE;
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integer scale = 1;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="prfh_i_p_bz_d_64_scaled, prfh_i_p_bz_d_x32_scaled, prfh_i_p_bz_s_x32_scaled" symboldefcount="1">
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<symbol link="sa_prfop"><prfop></symbol>
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<definition encodedin="prfop">
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<intro>Is the prefetch operation specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">prfop</entry>
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<entry class="symbol"><prfop></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0000</entry>
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<entry class="symbol">PLDL1KEEP</entry>
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</row>
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<row>
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<entry class="bitfield">0001</entry>
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<entry class="symbol">PLDL1STRM</entry>
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</row>
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<row>
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<entry class="bitfield">0010</entry>
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<entry class="symbol">PLDL2KEEP</entry>
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</row>
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<row>
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<entry class="bitfield">0011</entry>
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<entry class="symbol">PLDL2STRM</entry>
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</row>
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<row>
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<entry class="bitfield">0100</entry>
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<entry class="symbol">PLDL3KEEP</entry>
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</row>
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<row>
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<entry class="bitfield">0101</entry>
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<entry class="symbol">PLDL3STRM</entry>
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</row>
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<row>
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<entry class="bitfield">x11x</entry>
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<entry class="symbol">#uimm4</entry>
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</row>
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<row>
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<entry class="bitfield">1000</entry>
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<entry class="symbol">PSTL1KEEP</entry>
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</row>
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<row>
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<entry class="bitfield">1001</entry>
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<entry class="symbol">PSTL1STRM</entry>
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</row>
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<row>
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<entry class="bitfield">1010</entry>
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<entry class="symbol">PSTL2KEEP</entry>
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</row>
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<row>
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<entry class="bitfield">1011</entry>
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<entry class="symbol">PSTL2STRM</entry>
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</row>
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<row>
|
|
<entry class="bitfield">1100</entry>
|
|
<entry class="symbol">PSTL3KEEP</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1101</entry>
|
|
<entry class="symbol">PSTL3STRM</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="prfh_i_p_bz_d_64_scaled, prfh_i_p_bz_d_x32_scaled, prfh_i_p_bz_s_x32_scaled" symboldefcount="1">
|
|
<symbol link="sa_pg"><Pg></symbol>
|
|
<account encodedin="Pg">
|
|
<intro>
|
|
<para>Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="prfh_i_p_bz_d_64_scaled, prfh_i_p_bz_d_x32_scaled, prfh_i_p_bz_s_x32_scaled" symboldefcount="1">
|
|
<symbol link="sa_xn_sp"><Xn|SP></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="prfh_i_p_bz_d_64_scaled, prfh_i_p_bz_d_x32_scaled, prfh_i_p_bz_s_x32_scaled" symboldefcount="1">
|
|
<symbol link="sa_zm"><Zm></symbol>
|
|
<account encodedin="Zm">
|
|
<intro>
|
|
<para>Is the name of the offset scalable vector register, encoded in the "Zm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="prfh_i_p_bz_d_x32_scaled, prfh_i_p_bz_s_x32_scaled" symboldefcount="1">
|
|
<symbol link="sa_mod"><mod></symbol>
|
|
<definition encodedin="xs">
|
|
<intro>Is the index extend and shift specifier, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">xs</entry>
|
|
<entry class="symbol"><mod></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">UXTW</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">SXTW</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="PRFH-I.P.BZ-S.x32.scaled" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckNonStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
|
|
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
|
constant integer PL = VL DIV 8;
|
|
constant integer elements = VL DIV esize;
|
|
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
|
bits(64) base;
|
|
bits(VL) offset;
|
|
|
|
if <a link="impl-aarch64.AnyActiveElement.2" file="shared_pseudocode.xml" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then
|
|
base = if n == 31 then <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[] else <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
|
|
offset = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
|
|
|
for e = 0 to elements-1
|
|
if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
|
integer off = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[offset, e, esize]<offs_size-1:0>, offs_unsigned);
|
|
bits(64) addr = base + (off << scale);
|
|
<a link="impl-shared.Hint_Prefetch.4" file="shared_pseudocode.xml" hover="function: Hint_Prefetch(bits(64) address, PrefetchHint hint, integer target, boolean stream)">Hint_Prefetch</a>(addr, pref_hint, level, stream);</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|