mirror of
https://github.com/pound-emu/ballistic.git
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134 lines
7.1 KiB
XML
134 lines
7.1 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="RAX1_advsimd" title="RAX1 -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="RAX1" />
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</docvars>
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<heading>RAX1</heading>
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<desc>
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<brief>
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<para>Rotate and Exclusive-OR</para>
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</brief>
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<authored>
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<para>Rotate and Exclusive-OR rotates each 64-bit element of the 128-bit vector in a source SIMD&FP register left by 1, performs a bitwise exclusive-OR of the resulting 128-bit vector and the vector in another source SIMD&FP register, and writes the result to the destination SIMD&FP register.</para>
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<para>This instruction is implemented only when <xref linkend="v8.2.SHA3">FEAT_SHA3</xref> is implemented.</para>
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</authored>
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</desc>
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<operationalnotes>
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<para>If PSTATE.DIT is 1:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Advanced SIMD" oneof="1" id="iclass_advsimd" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="RAX1" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_SHA3" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/vector/crypto/sha3/rax1">
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<box hibit="31" width="11" settings="11">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Rm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" settings="1">
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<c>1</c>
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</box>
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<box hibit="14" name="O" settings="1">
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<c>0</c>
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</box>
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<box hibit="13" width="2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="11" width="2" name="opcode" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="RAX1_VVV2_cryptosha512_3" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="RAX1" />
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</docvars>
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<asmtemplate><text>RAX1 </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.2D, </text><a link="sa_vn" hover="First SIMD&FP source register (field "Rn")"><Vn></a><text>.2D, </text><a link="sa_vm" hover="Second SIMD&FP source register (field "Rm")"><Vm></a><text>.2D</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/crypto/sha3/rax1" mylink="aarch64.instrs.vector.crypto.sha3.rax1" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveSHA3Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA3Ext()">HaveSHA3Ext</a>() then UNDEFINED;
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="RAX1_VVV2_cryptosha512_3" symboldefcount="1">
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<symbol link="sa_vd"><Vd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="RAX1_VVV2_cryptosha512_3" symboldefcount="1">
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<symbol link="sa_vn"><Vn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the name of the first SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="RAX1_VVV2_cryptosha512_3" symboldefcount="1">
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<symbol link="sa_vm"><Vm></symbol>
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<account encodedin="Rm">
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<intro>
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<para>Is the name of the second SIMD&FP source register, encoded in the "Rm" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/crypto/sha3/rax1" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="AArch64.CheckFPAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
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bits(128) Vm = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, 128];
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bits(128) Vn = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, 128];
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<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = Vn EOR (<a link="impl-shared.ROL.2" file="shared_pseudocode.xml" hover="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(Vm<127:64>,1):<a link="impl-shared.ROL.2" file="shared_pseudocode.xml" hover="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(Vm<63:0>, 1));</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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