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archived-ballistic/spec/arm64_xml/rdffrs_p_p_f.xml
Ronald Caesar 26a677f8b4 decoder: Add ARM specification docs
Signed-off-by: Ronald Caesar <github43132@proton.me>
2025-12-12 18:11:36 -04:00

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<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<instructionsection id="rdffrs_p_p_f" title="RDFFRS" type="instruction">
<docvars>
<docvar key="cond-setting" value="s" />
<docvar key="instr-class" value="sve" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="RDFFRS" />
</docvars>
<heading>RDFFRS</heading>
<desc>
<brief>Return predicate of succesfully loaded elements, setting the condition flags</brief>
<description>
<para>Read the first-fault register (<asm-code>FFR</asm-code>) and place active elements in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the <arm-defined-word>First</arm-defined-word> (N), <arm-defined-word>None</arm-defined-word> (Z), <arm-defined-word>!Last</arm-defined-word> (C) condition flags based on the predicate result, and the V flag to zero.</para>
<para>This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.</para>
</description>
<status>Green</status>
<predicated>True</predicated>
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
<sm_policy>SM_0_only</sm_policy>
</desc>
<alias_list howmany="0"></alias_list>
<classes>
<iclass name="Setting the condition flags" oneof="1" id="iclass_s" no_encodings="1" isa="A64">
<docvars>
<docvar key="cond-setting" value="s" />
<docvar key="instr-class" value="sve" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="RDFFRS" />
</docvars>
<iclassintro count="1"></iclassintro>
<regdiagram form="32" psname="RDFFRS-P.P.F-_" tworows="1">
<box hibit="31" width="8" settings="8">
<c>0</c>
<c>0</c>
<c>1</c>
<c>0</c>
<c>0</c>
<c>1</c>
<c>0</c>
<c>1</c>
</box>
<box hibit="23" name="op" settings="1">
<c>0</c>
</box>
<box hibit="22" name="S" usename="1" settings="1">
<c>1</c>
</box>
<box hibit="21" width="12" settings="12">
<c>0</c>
<c>1</c>
<c>1</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>0</c>
<c>0</c>
</box>
<box hibit="9" settings="1">
<c>0</c>
</box>
<box hibit="8" width="4" name="Pg" usename="1">
<c colspan="4"></c>
</box>
<box hibit="4" settings="1">
<c>0</c>
</box>
<box hibit="3" width="4" name="Pd" usename="1">
<c colspan="4"></c>
</box>
</regdiagram>
<encoding name="rdffrs_p_p_f_" oneofinclass="1" oneof="1" label="">
<docvars>
<docvar key="cond-setting" value="s" />
<docvar key="instr-class" value="sve" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="RDFFRS" />
</docvars>
<asmtemplate><text>RDFFRS </text><a link="sa_pd" hover="Destination scalable predicate register (field &quot;Pd&quot;)">&lt;Pd&gt;</a><text>.B, </text><a link="sa_pg" hover="Governing scalable predicate register (field &quot;Pg&quot;)">&lt;Pg&gt;</a><text>/Z</text></asmtemplate>
</encoding>
<ps_section howmany="1">
<ps name="RDFFRS-P.P.F-_" mylink="RDFFRS-P.P.F-_" enclabels="" sections="1" secttype="noheading">
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pd);
boolean setflags = TRUE;</pstext>
</ps>
</ps_section>
</iclass>
</classes>
<explanations scope="all">
<explanation enclist="rdffrs_p_p_f_" symboldefcount="1">
<symbol link="sa_pd">&lt;Pd&gt;</symbol>
<account encodedin="Pd">
<intro>
<para>Is the name of the destination scalable predicate register, encoded in the "Pd" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="rdffrs_p_p_f_" symboldefcount="1">
<symbol link="sa_pg">&lt;Pg&gt;</symbol>
<account encodedin="Pg">
<intro>
<para>Is the name of the governing scalable predicate register, encoded in the "Pg" field.</para>
</intro>
</account>
</explanation>
</explanations>
<ps_section howmany="1">
<ps name="RDFFRS-P.P.F-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckNonStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
constant integer PL = VL DIV 8;
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
bits(PL) ffr = <a link="impl-aarch64.FFR.read.1" file="shared_pseudocode.xml" hover="accessor: bits(width) FFR[integer width]">FFR</a>[PL];
bits(PL) result = ffr AND mask;
if setflags then
PSTATE.&lt;N,Z,C,V&gt; = <a link="impl-aarch64.PredTest.3" file="shared_pseudocode.xml" hover="function: bits(4) PredTest(bits(N) mask, bits(N) result, integer esize)">PredTest</a>(mask, result, 8);
<a link="impl-aarch64.P.write.2" file="shared_pseudocode.xml" hover="accessor: P[integer n, integer width] = bits(width) value">P</a>[d, PL] = result;</pstext>
</ps>
</ps_section>
</instructionsection>