mirror of
https://github.com/pound-emu/ballistic.git
synced 2026-01-31 01:15:21 +01:00
279 lines
14 KiB
XML
279 lines
14 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
|
|
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
|
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
|
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
|
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
|
|
|
<instructionsection id="SABDL_advsimd" title="SABDL, SABDL2 -- A64" type="instruction">
|
|
<docvars>
|
|
<docvar key="advsimd-reguse" value="3reg-diff" />
|
|
<docvar key="advsimd-type" value="simd" />
|
|
<docvar key="instr-class" value="advsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="SABDL" />
|
|
</docvars>
|
|
<heading>SABDL, SABDL2</heading>
|
|
<desc>
|
|
<brief>
|
|
<para>Signed Absolute Difference Long</para>
|
|
</brief>
|
|
<authored>
|
|
<para>Signed Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.</para>
|
|
<para>The <instruction>SABDL</instruction> instruction extracts each source vector from the lower half of each source register. The <instruction>SABDL2</instruction> instruction extracts each source vector from the upper half of each source register.</para>
|
|
<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
|
|
</authored>
|
|
</desc>
|
|
<operationalnotes>
|
|
<para>If PSTATE.DIT is 1:</para>
|
|
<list type="unordered">
|
|
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
|
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
|
</list>
|
|
</operationalnotes>
|
|
<alias_list howmany="0"></alias_list>
|
|
<classes>
|
|
<iclass name="Three registers, not all the same type" oneof="1" id="iclass_3reg_diff" no_encodings="1" isa="A64">
|
|
<docvars>
|
|
<docvar key="advsimd-reguse" value="3reg-diff" />
|
|
<docvar key="advsimd-type" value="simd" />
|
|
<docvar key="instr-class" value="advsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="SABDL" />
|
|
</docvars>
|
|
<iclassintro count="1"></iclassintro>
|
|
<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/binary/disparate/diff" tworows="1">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="U" usename="1" settings="1" psbits="x">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="2" name="opcode[3:2]" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" name="op" usename="1" settings="1" psbits="x">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" name="opcode[0]" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="SABDL_asimddiff_L" oneofinclass="1" oneof="1" label="">
|
|
<docvars>
|
|
<docvar key="advsimd-reguse" value="3reg-diff" />
|
|
<docvar key="advsimd-type" value="simd" />
|
|
<docvar key="instr-class" value="advsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="SABDL" />
|
|
</docvars>
|
|
<asmtemplate><text>SABDL</text><a link="sa_2" hover="Second and upper half specifier (field "Q")">{2}</a><text> </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_ta" hover="Arrangement specifier (field "size") [2D,4S,8H]"><Ta></a><text>, </text><a link="sa_vn" hover="First SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_tb" hover="Arrangement specifier (field "size:Q") [2S,4H,4S,8B,8H,16B]"><Tb></a><text>, </text><a link="sa_vm" hover="Second SIMD&FP source register (field "Rm")"><Vm></a><text>.</text><a link="sa_tb" hover="Arrangement specifier (field "size:Q") [2S,4H,4S,8B,8H,16B]"><Tb></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/vector/arithmetic/binary/disparate/diff" mylink="aarch64.instrs.vector.arithmetic.binary.disparate.diff" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
|
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
|
|
|
if size == '11' then UNDEFINED;
|
|
integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
|
integer datasize = 64;
|
|
integer part = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q);
|
|
integer elements = datasize DIV esize;
|
|
|
|
boolean accumulate = (op == '0');
|
|
boolean unsigned = (U == '1');</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="SABDL_asimddiff_L" symboldefcount="1">
|
|
<symbol link="sa_2">2</symbol>
|
|
<definition encodedin="Q">
|
|
<intro>Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">Q</entry>
|
|
<entry class="symbol">2</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">[absent]</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">[present]</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="SABDL_asimddiff_L" symboldefcount="1">
|
|
<symbol link="sa_vd"><Vd></symbol>
|
|
<account encodedin="Rd">
|
|
<intro>
|
|
<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="SABDL_asimddiff_L" symboldefcount="1">
|
|
<symbol link="sa_ta"><Ta></symbol>
|
|
<definition encodedin="size">
|
|
<intro>Is an arrangement specifier, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">size</entry>
|
|
<entry class="symbol"><Ta></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8H</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">4S</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">2D</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="SABDL_asimddiff_L" symboldefcount="1">
|
|
<symbol link="sa_vn"><Vn></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the name of the first SIMD&FP source register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="SABDL_asimddiff_L" symboldefcount="1">
|
|
<symbol link="sa_tb"><Tb></symbol>
|
|
<definition encodedin="size:Q">
|
|
<intro>Is an arrangement specifier, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">size</entry>
|
|
<entry class="bitfield">Q</entry>
|
|
<entry class="symbol"><Tb></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">8B</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">16B</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">4H</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">8H</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">2S</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">4S</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="bitfield">x</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="SABDL_asimddiff_L" symboldefcount="1">
|
|
<symbol link="sa_vm"><Vm></symbol>
|
|
<account encodedin="Rm">
|
|
<intro>
|
|
<para>Is the name of the second SIMD&FP source register, encoded in the "Rm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/vector/arithmetic/binary/disparate/diff" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
|
|
bits(datasize) operand1 = <a link="impl-aarch64.Vpart.read.3" file="shared_pseudocode.xml" hover="accessor: bits(width) Vpart[integer n, integer part, integer width]">Vpart</a>[n, part, datasize];
|
|
bits(datasize) operand2 = <a link="impl-aarch64.Vpart.read.3" file="shared_pseudocode.xml" hover="accessor: bits(width) Vpart[integer n, integer part, integer width]">Vpart</a>[m, part, datasize];
|
|
bits(2*datasize) result;
|
|
integer element1;
|
|
integer element2;
|
|
bits(2*esize) absdiff;
|
|
|
|
result = if accumulate then <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[d, 2*datasize] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(2*datasize);
|
|
for e = 0 to elements-1
|
|
element1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
|
|
element2 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
|
|
absdiff = <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(element1 - element2)<2*esize-1:0>;
|
|
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 2*esize] + absdiff;
|
|
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 2*datasize] = result;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|