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Ronald Caesar 26a677f8b4 decoder: Add ARM specification docs
Signed-off-by: Ronald Caesar <github43132@proton.me>
2025-12-12 18:11:36 -04:00

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<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<instructionsection id="SETF" title="SETF8, SETF16 -- A64" type="instruction">
<docvars>
<docvar key="instr-class" value="general" />
<docvar key="isa" value="A64" />
</docvars>
<heading>SETF8, SETF16</heading>
<desc>
<brief>
<para>Evaluation of 8 or 16 bit flag values</para>
</brief>
<authored>
<para>Set the PSTATE.NZV flags based on the value in the specified general-purpose register. <instruction>SETF8</instruction> treats the value as an 8 bit value, and <instruction>SETF16</instruction> treats the value as an 16 bit value.</para>
<para>The PSTATE.C flag is not affected by these instructions.</para>
</authored>
</desc>
<operationalnotes>
<para>If PSTATE.DIT is 1:</para>
<list type="unordered">
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
</list>
</operationalnotes>
<alias_list howmany="0"></alias_list>
<classes>
<iclass name="Integer" oneof="1" id="iclass_general" no_encodings="2" isa="A64">
<docvars>
<docvar key="instr-class" value="general" />
<docvar key="isa" value="A64" />
</docvars>
<iclassintro count="2"></iclassintro>
<arch_variants>
<arch_variant name="ARMv8.4" feature="FEAT_FlagM" />
</arch_variants>
<regdiagram form="32" psname="aarch64/instrs/integer/flags/setf" tworows="1">
<box hibit="31" name="sf" usename="1" settings="1" psbits="x">
<c>0</c>
</box>
<box hibit="30" name="op" settings="1">
<c>0</c>
</box>
<box hibit="29" name="S" settings="1">
<c>1</c>
</box>
<box hibit="28" width="8" settings="8">
<c>1</c>
<c>1</c>
<c>0</c>
<c>1</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>0</c>
</box>
<box hibit="20" width="6" name="opcode2" settings="6">
<c>0</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>0</c>
</box>
<box hibit="14" name="sz" usename="1">
<c></c>
</box>
<box hibit="13" width="4" settings="4">
<c>0</c>
<c>0</c>
<c>1</c>
<c>0</c>
</box>
<box hibit="9" width="5" name="Rn" usename="1">
<c colspan="5"></c>
</box>
<box hibit="4" name="o3" settings="1">
<c>0</c>
</box>
<box hibit="3" width="4" name="mask" settings="4">
<c>1</c>
<c>1</c>
<c>0</c>
<c>1</c>
</box>
</regdiagram>
<encoding name="SETF8_only_setf" oneofinclass="2" oneof="2" label="SETF8" bitdiffs="sz == 0">
<docvars>
<docvar key="instr-class" value="general" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="SETF8" />
</docvars>
<box hibit="14" width="1" name="sz">
<c>0</c>
</box>
<asmtemplate><text>SETF8 </text><a link="sa_wn" hover="32-bit general-purpose source register (field &quot;Rn&quot;)">&lt;Wn&gt;</a></asmtemplate>
</encoding>
<encoding name="SETF16_only_setf" oneofinclass="2" oneof="2" label="SETF16" bitdiffs="sz == 1">
<docvars>
<docvar key="instr-class" value="general" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="SETF16" />
</docvars>
<box hibit="14" width="1" name="sz">
<c>1</c>
</box>
<asmtemplate><text>SETF16 </text><a link="sa_wn" hover="32-bit general-purpose source register (field &quot;Rn&quot;)">&lt;Wn&gt;</a></asmtemplate>
</encoding>
<ps_section howmany="1">
<ps name="aarch64/instrs/integer/flags/setf" mylink="aarch64.instrs.integer.flags.setf" enclabels="" sections="1" secttype="noheading">
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFlagManipulateExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveFlagManipulateExt()">HaveFlagManipulateExt</a>() || sf != '0' then UNDEFINED;
integer msb = if sz=='1' then 15 else 7;
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</pstext>
</ps>
</ps_section>
</iclass>
</classes>
<explanations scope="all">
<explanation enclist="SETF8_only_setf, SETF16_only_setf" symboldefcount="1">
<symbol link="sa_wn">&lt;Wn&gt;</symbol>
<account encodedin="Rn">
<intro>
<para>Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field.</para>
</intro>
</account>
</explanation>
</explanations>
<ps_section howmany="1">
<ps name="aarch64/instrs/integer/flags/setf" mylink="execute" enclabels="" sections="1" secttype="Operation">
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(32) tmpreg = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 32];
PSTATE.N = tmpreg&lt;msb&gt;;
PSTATE.Z = if (tmpreg&lt;msb:0&gt; == <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(msb+1)) then '1' else '0';
PSTATE.V = tmpreg&lt;msb+1&gt; EOR tmpreg&lt;msb&gt;;
//PSTATE.C unchanged;</pstext>
</ps>
</ps_section>
</instructionsection>