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383 lines
18 KiB
XML
383 lines
18 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="SHL_advsimd" title="SHL -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SHL" />
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</docvars>
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<heading>SHL</heading>
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<desc>
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<brief>
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<para>Shift Left (immediate)</para>
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</brief>
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<authored>
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<para>Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.</para>
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<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
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</authored>
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</desc>
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<operationalnotes>
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<para>If PSTATE.DIT is 1:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from 2 classes:</txt>
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<a href="#iclass_sisd">Scalar</a>
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<txt> and </txt>
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<a href="#iclass_simd">Vector</a>
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</classesintro>
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<iclass name="Scalar" oneof="2" id="iclass_sisd" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-type" value="sisd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SHL" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/vector/shift/left/sisd" tworows="1">
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<box hibit="31" width="2" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="29" name="U" settings="1">
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<c>0</c>
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</box>
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<box hibit="28" width="6" settings="6">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="22" width="4" name="immh" usename="1" settings="4" constraint="!= 0000" psbits="xxxx">
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<c colspan="4">!= 0000</c>
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</box>
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<box hibit="18" width="3" name="immb" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="15" width="5" name="opcode" settings="5">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="10" settings="1">
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<c>1</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="SHL_asisdshf_R" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="advsimd-type" value="sisd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SHL" />
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</docvars>
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<asmtemplate><text>SHL </text><a link="sa_v" hover="Width specifier (field "immh") [D]"><V></a><a link="sa_d" hover="SIMD&FP destination register number (field "Rd")"><d></a><text>, </text><a link="sa_v" hover="Width specifier (field "immh") [D]"><V></a><a link="sa_n" hover="First SIMD&FP source register number (field "Rn")"><n></a><text>, #</text><a link="sa_shift_1" hover="Left shift amount [0-63] (field "immh:immb") [(UInt(immh:immb)-64)]"><shift></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/shift/left/sisd" mylink="aarch64.instrs.vector.shift.left.sisd" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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if immh<3> != '1' then UNDEFINED;
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integer esize = 8 << 3;
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integer datasize = esize;
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integer elements = 1;
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integer shift = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(immh:immb) - esize;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Vector" oneof="2" id="iclass_simd" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-type" value="simd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SHL" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/vector/shift/left/simd" tworows="1">
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<box hibit="31" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="29" name="U" settings="1">
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<c>0</c>
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</box>
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<box hibit="28" width="6" settings="6">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="22" width="4" name="immh" usename="1" settings="4" constraint="!= 0000">
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<c colspan="4">!= 0000</c>
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</box>
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<box hibit="18" width="3" name="immb" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="15" width="5" name="opcode" settings="5">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="10" settings="1">
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<c>1</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="SHL_asimdshf_R" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="advsimd-type" value="simd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SHL" />
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</docvars>
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<asmtemplate><text>SHL </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "immh:Q") [2D,2S,4H,4S,8B,8H,16B,SEE(asimdimm)]"><T></a><text>, </text><a link="sa_vn" hover="SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "immh:Q") [2D,2S,4H,4S,8B,8H,16B,SEE(asimdimm)]"><T></a><text>, #</text><a link="sa_shift" hover="Left shift amount [0-the element width in bits minus 1] (field "immh:immb") [(UInt(immh:immb)-8),(UInt(immh:immb)-16),(UInt(immh:immb)-32),(UInt(immh:immb)-64),SEE(asimdimm)]"><shift></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/shift/left/simd" mylink="aarch64.instrs.vector.shift.left.simd" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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if immh == '0000' then <a link="asimdimm" file="encodingindex.xml" hover="handled by an instruction in the 'Advanced SIMD modified immediate' class">SEE(asimdimm)</a>;
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if immh<3>:Q == '10' then UNDEFINED;
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integer esize = 8 << <a link="impl-shared.HighestSetBit.1" file="shared_pseudocode.xml" hover="function: integer HighestSetBit(bits(N) x)">HighestSetBit</a>(immh);
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integer datasize = if Q == '1' then 128 else 64;
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integer elements = datasize DIV esize;
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integer shift = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(immh:immb) - esize;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="SHL_asisdshf_R" symboldefcount="1">
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<symbol link="sa_v"><V></symbol>
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<definition encodedin="immh">
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<intro>Is a width specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">immh</entry>
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<entry class="symbol"><V></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0xxx</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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<row>
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<entry class="bitfield">1xxx</entry>
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<entry class="symbol">D</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="SHL_asisdshf_R" symboldefcount="1">
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<symbol link="sa_d"><d></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the number of the SIMD&FP destination register, in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="SHL_asisdshf_R" symboldefcount="1">
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<symbol link="sa_n"><n></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the number of the first SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="SHL_asimdshf_R" symboldefcount="1">
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<symbol link="sa_vd"><Vd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="SHL_asimdshf_R" symboldefcount="1">
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<symbol link="sa_t"><T></symbol>
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<definition encodedin="immh:Q">
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<intro>Is an arrangement specifier, </intro>
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<table class="valuetable">
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<tgroup cols="3">
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<thead>
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<row>
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<entry class="bitfield">immh</entry>
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<entry class="bitfield">Q</entry>
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<entry class="symbol"><T></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0000</entry>
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<entry class="bitfield">x</entry>
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<entry class="symbol" iclasslink="asimdimm" iclasslinkfile="encodingindex.xml">SEE Advanced SIMD modified immediate</entry>
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</row>
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<row>
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<entry class="bitfield">0001</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">8B</entry>
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</row>
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<row>
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<entry class="bitfield">0001</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">16B</entry>
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</row>
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<row>
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<entry class="bitfield">001x</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">4H</entry>
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</row>
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<row>
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<entry class="bitfield">001x</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">8H</entry>
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</row>
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<row>
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<entry class="bitfield">01xx</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">2S</entry>
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</row>
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<row>
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<entry class="bitfield">01xx</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">4S</entry>
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</row>
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<row>
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<entry class="bitfield">1xxx</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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<row>
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<entry class="bitfield">1xxx</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">2D</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="SHL_asimdshf_R" symboldefcount="1">
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<symbol link="sa_vn"><Vn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the name of the SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="SHL_asisdshf_R" symboldefcount="1">
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<symbol link="sa_shift_1"><shift></symbol>
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<definition encodedin="immh:immb">
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<intro>For the scalar variant: is the left shift amount, in the range 0 to 63, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">immh</entry>
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<entry class="symbol"><shift></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0xxx</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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<row>
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<entry class="bitfield">1xxx</entry>
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<entry class="symbol">(UInt(immh:immb)-64)</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="SHL_asimdshf_R" symboldefcount="2">
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<symbol link="sa_shift"><shift></symbol>
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<definition encodedin="immh:immb">
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<intro>For the vector variant: is the left shift amount, in the range 0 to the element width in bits minus 1, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">immh</entry>
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<entry class="symbol"><shift></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0000</entry>
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<entry class="symbol" iclasslink="asimdimm" iclasslinkfile="encodingindex.xml">SEE Advanced SIMD modified immediate</entry>
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</row>
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<row>
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<entry class="bitfield">0001</entry>
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<entry class="symbol">(UInt(immh:immb)-8)</entry>
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</row>
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<row>
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<entry class="bitfield">001x</entry>
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<entry class="symbol">(UInt(immh:immb)-16)</entry>
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</row>
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<row>
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<entry class="bitfield">01xx</entry>
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<entry class="symbol">(UInt(immh:immb)-32)</entry>
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</row>
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<row>
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<entry class="bitfield">1xxx</entry>
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<entry class="symbol">(UInt(immh:immb)-64)</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/shift/left/sisd" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
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bits(datasize) operand = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
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bits(datasize) result;
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for e = 0 to elements-1
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
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<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, datasize] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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