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380 lines
21 KiB
XML
380 lines
21 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="smlsl_za_zzv" title="SMLSL (multiple and single vector)" type="instruction">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SMLSL" />
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</docvars>
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<heading>SMLSL (multiple and single vector)</heading>
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<desc>
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<brief>Multi-vector signed integer multiply-subtract long by vector</brief>
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<description>
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<para>The instruction operates on one, two, or four ZA double-vector groups.</para>
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<para>This signed integer multiply-subtract long instruction multiplies each signed 16-bit element in the one, two, or four first source vectors with each signed 16-bit element in the second source vector, widens each product to 32-bits and destructively subtracts these values from the corresponding 32-bit elements of the one, two, or four ZA double-vector groups. The lowest of the two consecutive vector numbers forming the double-vector group within all, each half, or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo all, half, or quarter the number of ZA array vectors.</para>
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<para>The <arm-defined-word>vector group</arm-defined-word> symbol, <syntax>VGx2</syntax> or <syntax>VGx4</syntax>, indicates that the ZA operand consists of two or four ZA double-vector groups respectively. The <arm-defined-word>vector group</arm-defined-word> symbol is preferred for disassembly, but optional in assembler source code.</para>
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<para>This instruction is unpredicated.</para>
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</description>
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<status>Green</status>
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<predicated>False</predicated>
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<sm_policy>SM_1_only</sm_policy>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="3">
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<txt>It has encodings from 3 classes:</txt>
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<a href="#iclass_sme_vgx1_double">One ZA double-vector</a>
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<txt>, </txt>
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<a href="#iclass_sme_vgx2_double">Two ZA double-vectors</a>
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<txt> and </txt>
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<a href="#iclass_sme_vgx4_double">Four ZA double-vectors</a>
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</classesintro>
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<iclass name="One ZA double-vector" oneof="3" id="iclass_sme_vgx1_double" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SMLSL" />
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<docvar key="sme-multireg" value="sme-vgx1-double" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
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</arch_variants>
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<regdiagram form="32" psname="SMLSL-ZA.ZZV-1" tworows="1">
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<box hibit="31" width="12" settings="12">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Zm" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" settings="1">
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<c>0</c>
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</box>
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<box hibit="14" width="2" name="Rv" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="12" width="3" settings="3">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" name="U" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" name="S" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="2" width="3" name="off3" usename="1">
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<c colspan="3"></c>
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</box>
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</regdiagram>
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<encoding name="smlsl_za_zzv_1" oneofinclass="1" oneof="3" label="">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SMLSL" />
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<docvar key="sme-multireg" value="sme-vgx1-double" />
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</docvars>
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<asmtemplate><text>SMLSL ZA.S[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offsf" hover="Vector select offset, pointing to first of two consecutive vectors, encoded as "off3" field times 2 (field off3)"><offsf></a><text>:</text><a link="sa_offsl" hover="Vector select offset, pointing to last of two consecutive vectors, encoded as "off3" field times 2 plus 1 (field off3)"><offsl></a><text>], </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.H, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field "Zm")"><Zm></a><text>.H</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="SMLSL-ZA.ZZV-1" mylink="SMLSL-ZA.ZZV-1" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
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constant integer esize = 32;
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integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
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integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off3:'0');
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constant integer nreg = 1;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Two ZA double-vectors" oneof="3" id="iclass_sme_vgx2_double" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SMLSL" />
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<docvar key="sme-multireg" value="sme-vgx2-double" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
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</arch_variants>
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<regdiagram form="32" psname="SMLSL-ZA.ZZV-2x1" tworows="1">
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<box hibit="31" width="12" settings="12">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Zm" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" settings="1">
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<c>0</c>
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</box>
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<box hibit="14" width="2" name="Rv" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="12" width="3" settings="3">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" name="U" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" name="S" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="2" settings="1">
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<c>0</c>
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</box>
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<box hibit="1" width="2" name="off2" usename="1">
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<c colspan="2"></c>
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</box>
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</regdiagram>
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<encoding name="smlsl_za_zzv_2x1" oneofinclass="1" oneof="3" label="">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SMLSL" />
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<docvar key="sme-multireg" value="sme-vgx2-double" />
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</docvars>
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<asmtemplate><text>SMLSL ZA.S[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offsf_1" hover="Vector select offset, pointing to first of two consecutive vectors, encoded as "off2" field times 2 (field off2)"><offsf></a><text>:</text><a link="sa_offsl_1" hover="Vector select offset, pointing to last of two consecutive vectors, encoded as "off2" field times 2 plus 1 (field off2)"><offsl></a><a>{, VGx2}</a><text>], </text><text>{</text><text> </text><a link="sa_zn1" hover="First scalable vector register of a multi-vector sequence, encoded as "Zn" (field Zn)"><Zn1></a><text>.H-</text><a link="sa_zn2" hover="Second scalable vector register of a multi-vector sequence (field Zn)"><Zn2></a><text>.H </text><text>}</text><text>, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field "Zm")"><Zm></a><text>.H</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="SMLSL-ZA.ZZV-2x1" mylink="SMLSL-ZA.ZZV-2x1" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
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constant integer esize = 32;
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integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
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integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off2:'0');
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constant integer nreg = 2;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Four ZA double-vectors" oneof="3" id="iclass_sme_vgx4_double" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SMLSL" />
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<docvar key="sme-multireg" value="sme-vgx4-double" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
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</arch_variants>
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<regdiagram form="32" psname="SMLSL-ZA.ZZV-4x1" tworows="1">
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<box hibit="31" width="12" settings="12">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Zm" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" settings="1">
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<c>0</c>
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</box>
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<box hibit="14" width="2" name="Rv" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="12" width="3" settings="3">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" name="U" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" name="S" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="2" settings="1">
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<c>0</c>
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</box>
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<box hibit="1" width="2" name="off2" usename="1">
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<c colspan="2"></c>
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</box>
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</regdiagram>
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<encoding name="smlsl_za_zzv_4x1" oneofinclass="1" oneof="3" label="">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SMLSL" />
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<docvar key="sme-multireg" value="sme-vgx4-double" />
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</docvars>
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<asmtemplate><text>SMLSL ZA.S[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offsf_1" hover="Vector select offset, pointing to first of two consecutive vectors, encoded as "off2" field times 2 (field off2)"><offsf></a><text>:</text><a link="sa_offsl_1" hover="Vector select offset, pointing to last of two consecutive vectors, encoded as "off2" field times 2 plus 1 (field off2)"><offsl></a><a>{, VGx4}</a><text>], </text><text>{</text><text> </text><a link="sa_zn1" hover="First scalable vector register of a multi-vector sequence, encoded as "Zn" (field Zn)"><Zn1></a><text>.H-</text><a link="sa_zn4" hover="Fourth scalable vector register of a multi-vector sequence (field Zn)"><Zn4></a><text>.H </text><text>}</text><text>, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field "Zm")"><Zm></a><text>.H</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="SMLSL-ZA.ZZV-4x1" mylink="SMLSL-ZA.ZZV-4x1" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
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constant integer esize = 32;
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integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
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integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off2:'0');
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constant integer nreg = 4;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="smlsl_za_zzv_1, smlsl_za_zzv_2x1, smlsl_za_zzv_4x1" symboldefcount="1">
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<symbol link="sa_wv"><Wv></symbol>
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<account encodedin="Rv">
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<intro>
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<para>Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="smlsl_za_zzv_1" symboldefcount="1">
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<symbol link="sa_offsf"><offsf></symbol>
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<account encodedin="off3">
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<docvars>
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<docvar key="sme-multireg" value="sme-vgx1-double" />
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</docvars>
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<intro>
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<para>For the one ZA double-vector variant: is the vector select offset, pointing to first of two consecutive vectors, encoded as "off3" field times 2.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="smlsl_za_zzv_2x1, smlsl_za_zzv_4x1" symboldefcount="2">
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<symbol link="sa_offsf_1"><offsf></symbol>
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<account encodedin="off2">
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<intro>
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<para>For the four ZA double-vectors and two ZA double-vectors variant: is the vector select offset, pointing to first of two consecutive vectors, encoded as "off2" field times 2.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="smlsl_za_zzv_1" symboldefcount="1">
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<symbol link="sa_offsl"><offsl></symbol>
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<account encodedin="off3">
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<docvars>
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<docvar key="sme-multireg" value="sme-vgx1-double" />
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</docvars>
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<intro>
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<para>For the one ZA double-vector variant: is the vector select offset, pointing to last of two consecutive vectors, encoded as "off3" field times 2 plus 1.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="smlsl_za_zzv_2x1, smlsl_za_zzv_4x1" symboldefcount="2">
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<symbol link="sa_offsl_1"><offsl></symbol>
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<account encodedin="off2">
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<intro>
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<para>For the four ZA double-vectors and two ZA double-vectors variant: is the vector select offset, pointing to last of two consecutive vectors, encoded as "off2" field times 2 plus 1.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="smlsl_za_zzv_1" symboldefcount="1">
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<symbol link="sa_zn"><Zn></symbol>
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<account encodedin="Zn">
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<intro>
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<para>Is the name of the first source scalable vector register, encoded in the "Zn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="smlsl_za_zzv_2x1, smlsl_za_zzv_4x1" symboldefcount="1">
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<symbol link="sa_zn1"><Zn1></symbol>
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<account encodedin="Zn">
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<intro>
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<para>Is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn".</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="smlsl_za_zzv_4x1" symboldefcount="1">
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<symbol link="sa_zn4"><Zn4></symbol>
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<account encodedin="Zn">
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<intro>
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<para>Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zn" plus 3 modulo 32.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="smlsl_za_zzv_2x1" symboldefcount="1">
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<symbol link="sa_zn2"><Zn2></symbol>
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<account encodedin="Zn">
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<intro>
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<para>Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zn" plus 1 modulo 32.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="smlsl_za_zzv_1, smlsl_za_zzv_2x1, smlsl_za_zzv_4x1" symboldefcount="1">
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<symbol link="sa_zm"><Zm></symbol>
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<account encodedin="Zm">
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<intro>
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<para>Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.</para>
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</intro>
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</account>
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|
</explanation>
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|
</explanations>
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|
<ps_section howmany="1">
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<ps name="SMLSL-ZA.ZZV-1" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEAndZAEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
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constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
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constant integer elements = VL DIV esize;
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integer vectors = VL DIV 8;
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integer vstride = vectors DIV nreg;
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bits(32) vbase = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[v, 32];
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integer vec = (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vbase) + offset) MOD vstride;
|
|
bits(VL) result;
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vec = vec - (vec MOD 2);
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|
|
|
for r = 0 to nreg-1
|
|
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[(n+r) MOD 32, VL];
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|
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
|
for i = 0 to 1
|
|
bits(VL) operand3 = <a link="impl-aarch64.ZAvector.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) ZAvector[integer index, integer width]">ZAvector</a>[vec + i, VL];
|
|
for e = 0 to elements-1
|
|
integer element1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * e + i, esize DIV 2]);
|
|
integer element2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * e + i, esize DIV 2]);
|
|
bits(esize) product = (element1 * element2)<esize-1:0>;
|
|
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
|
|
<a link="impl-aarch64.ZAvector.write.2" file="shared_pseudocode.xml" hover="accessor: ZAvector[integer index, integer width] = bits(width) value">ZAvector</a>[vec + i, VL] = result;
|
|
vec = vec + vstride;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|