mirror of
https://github.com/pound-emu/ballistic.git
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265 lines
12 KiB
XML
265 lines
12 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="sqincp_r_p_r" title="SQINCP (scalar)" type="instruction">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SQINCP" />
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</docvars>
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<heading>SQINCP (scalar)</heading>
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<desc>
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<brief>Signed saturating increment scalar by count of true predicate elements</brief>
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<description>
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<para>Counts the number of true elements in the source predicate and then uses the result to increment the scalar destination. The result is saturated to the source general-purpose register's signed integer range. A 32-bit saturated result is then sign-extended to 64 bits.</para>
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</description>
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<status>Green</status>
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<predicated>False</predicated>
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<affected_by_sme output="general-purpose register" />
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from 2 classes:</txt>
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<a href="#iclass_32_fsreg">32-bit</a>
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<txt> and </txt>
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<a href="#iclass_64_fsreg">64-bit</a>
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</classesintro>
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<iclass name="32-bit" oneof="2" id="iclass_32_fsreg" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="atomic-ops" value="SQINCP-32-fsreg" />
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SQINCP" />
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<docvar key="reg-type" value="32-fsreg" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="SQINCP-R.P.R-SX" tworows="1">
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<box hibit="31" width="8" settings="8">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="23" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="21" width="4" settings="4">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="17" name="D" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="16" name="U" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="15" width="5" settings="5">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="10" name="sf" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="9" name="op" settings="1">
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<c>0</c>
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</box>
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<box hibit="8" width="4" name="Pm" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="4" width="5" name="Rdn" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="sqincp_r_p_r_sx" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="atomic-ops" value="SQINCP-32-fsreg" />
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SQINCP" />
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<docvar key="reg-type" value="32-fsreg" />
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</docvars>
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<asmtemplate><text>SQINCP </text><a link="sa_xdn" hover="64-bit source and destination general-purpose register (field "Rdn")"><Xdn></a><text>, </text><a link="sa_pm" hover="Source scalable predicate register (field "Pm")"><Pm></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_wdn" hover="32-bit source and destination general-purpose register (field "Rdn")"><Wdn></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="SQINCP-R.P.R-SX" mylink="SQINCP-R.P.R-SX" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
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constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pm);
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integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn);
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boolean unsigned = FALSE;
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integer ssize = 32;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="64-bit" oneof="2" id="iclass_64_fsreg" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="atomic-ops" value="SQINCP-64-fsreg" />
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SQINCP" />
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<docvar key="reg-type" value="64-fsreg" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="SQINCP-R.P.R-X" tworows="1">
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<box hibit="31" width="8" settings="8">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="23" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="21" width="4" settings="4">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="17" name="D" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="16" name="U" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="15" width="5" settings="5">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="10" name="sf" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="9" name="op" settings="1">
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<c>0</c>
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</box>
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<box hibit="8" width="4" name="Pm" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="4" width="5" name="Rdn" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="sqincp_r_p_r_x" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="atomic-ops" value="SQINCP-64-fsreg" />
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SQINCP" />
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<docvar key="reg-type" value="64-fsreg" />
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</docvars>
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<asmtemplate><text>SQINCP </text><a link="sa_xdn" hover="64-bit source and destination general-purpose register (field "Rdn")"><Xdn></a><text>, </text><a link="sa_pm" hover="Source scalable predicate register (field "Pm")"><Pm></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="SQINCP-R.P.R-X" mylink="SQINCP-R.P.R-X" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
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constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pm);
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integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn);
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boolean unsigned = FALSE;
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integer ssize = 64;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="sqincp_r_p_r_sx, sqincp_r_p_r_x" symboldefcount="1">
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<symbol link="sa_xdn"><Xdn></symbol>
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<account encodedin="Rdn">
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<intro>
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<para>Is the 64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="sqincp_r_p_r_sx, sqincp_r_p_r_x" symboldefcount="1">
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<symbol link="sa_pm"><Pm></symbol>
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<account encodedin="Pm">
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<intro>
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<para>Is the name of the source scalable predicate register, encoded in the "Pm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="sqincp_r_p_r_sx, sqincp_r_p_r_x" symboldefcount="1">
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<symbol link="sa_t"><T></symbol>
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<definition encodedin="size">
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<intro>Is the size specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">size</entry>
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<entry class="symbol"><T></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="symbol">B</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="symbol">H</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="symbol">S</entry>
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</row>
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<row>
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<entry class="bitfield">11</entry>
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<entry class="symbol">D</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="sqincp_r_p_r_sx" symboldefcount="1">
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<symbol link="sa_wdn"><Wdn></symbol>
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<account encodedin="Rdn">
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<intro>
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<para>Is the 32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="SQINCP-R.P.R-SX" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
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constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
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constant integer PL = VL DIV 8;
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constant integer elements = VL DIV esize;
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bits(ssize) operand1 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[dn, ssize];
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bits(PL) operand2 = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[m, PL];
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bits(ssize) result;
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integer count = 0;
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for e = 0 to elements-1
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if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(operand2, e, esize) then
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count = count + 1;
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integer element = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(operand1, unsigned);
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(result, -) = <a link="impl-shared.SatQ.3" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element + count, ssize, unsigned);
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<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[dn, 64] = <a link="impl-shared.Extend.3" file="shared_pseudocode.xml" hover="function: bits(N) Extend(bits(M) x, integer N, boolean unsigned)">Extend</a>(result, 64, unsigned);</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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