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https://github.com/pound-emu/ballistic.git
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259 lines
12 KiB
XML
259 lines
12 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="sqincw_z_zs" title="SQINCW (vector)" type="instruction">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SQINCW" />
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<docvar key="sve-esize" value="esize-word" />
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</docvars>
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<heading>SQINCW (vector)</heading>
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<desc>
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<brief>Signed saturating increment vector by multiple of 32-bit predicate constraint element count</brief>
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<description>
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<para>Determines the number of active 32-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to increment all destination vector elements. The results are saturated to the 32-bit signed integer range.</para>
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<para>The named predicate constraint limits the number of active elements in a single predicate to:</para>
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<list type="unordered">
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<listitem>
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<content>A fixed number (<value>VL1</value> to <value>VL256</value>)</content>
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</listitem>
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<listitem>
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<content>The largest power of two (<value>POW2</value>)</content>
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</listitem>
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<listitem>
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<content>The largest multiple of three or four (<value>MUL3</value> or <value>MUL4</value>)</content>
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</listitem>
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<listitem>
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<content>All available, implicitly a multiple of two (<value>ALL</value>).</content>
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</listitem>
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</list>
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<para>Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.</para>
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</description>
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<status>Green</status>
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<predicated>False</predicated>
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<takes_movprfx>True</takes_movprfx>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SQINCW" />
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<docvar key="sve-esize" value="esize-word" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="SQINCW-Z.ZS-_" tworows="1">
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<box hibit="31" width="8" settings="8">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" name="size<1>" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="size<0>" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="imm4" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" settings="4">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="11" name="D" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="10" name="U" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="pattern" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zdn" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="sqincw_z_zs_" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SQINCW" />
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<docvar key="sve-esize" value="esize-word" />
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</docvars>
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<asmtemplate><text>SQINCW </text><a link="sa_zdn" hover="Source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.S</text><text>{</text><text>, </text><a link="sa_pattern" hover="Optional pattern specifier, default ALL (field "pattern") [#uimm5,ALL,MUL3,MUL4,POW2,VL1,VL2,VL3,VL4,VL5,VL6,VL7,VL8,VL16,VL32,VL64,VL128,VL256]"><pattern></a><text>{</text><text>, MUL #</text><a link="sa_imm" hover="Immediate multiplier [1-16], default 1 (field "imm4")"><imm></a><text>}</text><text>}</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="SQINCW-Z.ZS-_" mylink="SQINCW-Z.ZS-_" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
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constant integer esize = 32;
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integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
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bits(5) pat = pattern;
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integer imm = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm4) + 1;
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boolean unsigned = FALSE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="sqincw_z_zs_" symboldefcount="1">
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<symbol link="sa_zdn"><Zdn></symbol>
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<account encodedin="Zdn">
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<intro>
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<para>Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="sqincw_z_zs_" symboldefcount="1">
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<symbol link="sa_pattern"><pattern></symbol>
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<definition encodedin="pattern">
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<intro>Is the optional pattern specifier, defaulting to ALL, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">pattern</entry>
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<entry class="symbol"><pattern></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00000</entry>
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<entry class="symbol">POW2</entry>
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</row>
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<row>
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<entry class="bitfield">00001</entry>
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<entry class="symbol">VL1</entry>
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</row>
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<row>
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<entry class="bitfield">00010</entry>
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<entry class="symbol">VL2</entry>
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</row>
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<row>
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<entry class="bitfield">00011</entry>
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<entry class="symbol">VL3</entry>
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</row>
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<row>
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<entry class="bitfield">00100</entry>
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<entry class="symbol">VL4</entry>
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</row>
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<row>
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<entry class="bitfield">00101</entry>
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<entry class="symbol">VL5</entry>
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</row>
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<row>
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<entry class="bitfield">00110</entry>
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<entry class="symbol">VL6</entry>
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</row>
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<row>
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<entry class="bitfield">00111</entry>
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<entry class="symbol">VL7</entry>
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</row>
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<row>
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<entry class="bitfield">01000</entry>
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<entry class="symbol">VL8</entry>
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</row>
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<row>
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<entry class="bitfield">01001</entry>
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<entry class="symbol">VL16</entry>
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</row>
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<row>
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<entry class="bitfield">01010</entry>
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<entry class="symbol">VL32</entry>
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</row>
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<row>
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<entry class="bitfield">01011</entry>
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<entry class="symbol">VL64</entry>
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</row>
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<row>
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<entry class="bitfield">01100</entry>
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<entry class="symbol">VL128</entry>
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</row>
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<row>
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<entry class="bitfield">01101</entry>
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<entry class="symbol">VL256</entry>
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</row>
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<row>
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<entry class="bitfield">0111x</entry>
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<entry class="symbol">#uimm5</entry>
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</row>
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<row>
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<entry class="bitfield">101x1</entry>
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<entry class="symbol">#uimm5</entry>
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</row>
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<row>
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<entry class="bitfield">10110</entry>
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<entry class="symbol">#uimm5</entry>
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</row>
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<row>
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<entry class="bitfield">1x0x1</entry>
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<entry class="symbol">#uimm5</entry>
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</row>
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<row>
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<entry class="bitfield">1x010</entry>
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<entry class="symbol">#uimm5</entry>
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</row>
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<row>
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<entry class="bitfield">1xx00</entry>
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<entry class="symbol">#uimm5</entry>
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</row>
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<row>
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<entry class="bitfield">11101</entry>
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<entry class="symbol">MUL4</entry>
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</row>
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<row>
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<entry class="bitfield">11110</entry>
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<entry class="symbol">MUL3</entry>
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</row>
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<row>
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<entry class="bitfield">11111</entry>
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<entry class="symbol">ALL</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="sqincw_z_zs_" symboldefcount="1">
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<symbol link="sa_imm"><imm></symbol>
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<account encodedin="imm4">
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<intro>
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<para>Is the immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="SQINCW-Z.ZS-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
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constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
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constant integer elements = VL DIV esize;
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integer count = <a link="impl-aarch64.DecodePredCount.2" file="shared_pseudocode.xml" hover="function: integer DecodePredCount(bits(5) pattern, integer esize)">DecodePredCount</a>(pat, esize);
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bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
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bits(VL) result;
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for e = 0 to elements-1
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integer element1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
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(<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], -) = <a link="impl-shared.SatQ.3" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element1 + (count * imm), esize, unsigned);
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<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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