mirror of
https://github.com/pound-emu/ballistic.git
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319 lines
18 KiB
XML
319 lines
18 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="sqrdcmlah_z_zzzi" title="SQRDCMLAH (indexed)" type="instruction">
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<docvars>
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<docvar key="instr-class" value="sve2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SQRDCMLAH" />
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</docvars>
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<heading>SQRDCMLAH (indexed)</heading>
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<desc>
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<brief>Saturating rounding doubling complex integer multiply-add high with rotate (indexed)</brief>
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<description>
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<para>Multiply without saturation the duplicated real components for rotations 0 and 180, or imaginary components for rotations 90 and 270, of the integral numbers in each 128-bit segment of the first source vector by the specified complex number in the corresponding the second source vector segment rotated by 0, 90, 180 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation.</para>
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<para>Then double and add the products to the corresponding components of the complex numbers in the addend vector. Destructively place the most significant rounded half of the results in the corresponding elements of the addend vector. Each result element is saturated to the N-bit element's signed integer range -2<sup>(N-1) </sup> to (2<sup>(N-1) </sup>)-1. This instruction is unpredicated.</para>
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<para>These transformations permit the creation of a variety of multiply-add and multiply-subtract operations on complex numbers by combining two of these instructions with the same vector operands but with rotations that are 90 degrees apart.</para>
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<para>Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element.</para>
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</description>
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<status>Green</status>
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<predicated>False</predicated>
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<takes_movprfx>True</takes_movprfx>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from 2 classes:</txt>
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<a href="#iclass_of_halfwords">16-bit</a>
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<txt> and </txt>
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<a href="#iclass_of_words">32-bit</a>
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</classesintro>
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<iclass name="16-bit" oneof="2" id="iclass_of_halfwords" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="as-structure-org" value="of-halfwords" />
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<docvar key="instr-class" value="sve2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SQRDCMLAH" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="SQRDCMLAH-Z.ZZZi-H" tworows="1">
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<box hibit="31" width="8" settings="8">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" name="size<1>" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="size<0>" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="2" name="i2" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="18" width="3" name="Zm" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="15" width="4" settings="4">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="11" width="2" name="rot" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zda" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="sqrdcmlah_z_zzzi_h" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="as-structure-org" value="of-halfwords" />
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<docvar key="instr-class" value="sve2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SQRDCMLAH" />
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</docvars>
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<asmtemplate><text>SQRDCMLAH </text><a link="sa_zda" hover="Third source and destination scalable vector register (field "Zda")"><Zda></a><text>.H, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.H, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z7 (field "Zm")"><Zm></a><text>.H[</text><a link="sa_imm" hover="Element index [0-3] (field "i2")"><imm></a><text>], </text><a link="sa_const" hover="Const specifier (field "rot") [#0,#90,#180,#270]"><const></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="SQRDCMLAH-Z.ZZZi-H" mylink="SQRDCMLAH-Z.ZZZi-H" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
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constant integer esize = 16;
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integer index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(i2);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
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integer da = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zda);
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integer sel_a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rot<0>);
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integer sel_b = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(NOT(rot<0>));
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boolean sub_r = (rot<0> != rot<1>);
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boolean sub_i = (rot<1> == '1');</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="32-bit" oneof="2" id="iclass_of_words" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="as-structure-org" value="of-words" />
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<docvar key="instr-class" value="sve2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SQRDCMLAH" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="SQRDCMLAH-Z.ZZZi-S" tworows="1">
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<box hibit="31" width="8" settings="8">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" name="size<1>" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="size<0>" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" name="i1" usename="1">
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<c></c>
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</box>
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<box hibit="19" width="4" name="Zm" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" settings="4">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="11" width="2" name="rot" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zda" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="sqrdcmlah_z_zzzi_s" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="as-structure-org" value="of-words" />
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<docvar key="instr-class" value="sve2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SQRDCMLAH" />
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</docvars>
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<asmtemplate><text>SQRDCMLAH </text><a link="sa_zda" hover="Third source and destination scalable vector register (field "Zda")"><Zda></a><text>.S, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.S, </text><a link="sa_zm_1" hover="Second source scalable vector register Z0-Z15 (field "Zm")"><Zm></a><text>.S[</text><a link="sa_imm_1" hover="Element index [0-1] (field "i1")"><imm></a><text>], </text><a link="sa_const" hover="Const specifier (field "rot") [#0,#90,#180,#270]"><const></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="SQRDCMLAH-Z.ZZZi-S" mylink="SQRDCMLAH-Z.ZZZi-S" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
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constant integer esize = 32;
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integer index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(i1);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
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integer da = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zda);
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integer sel_a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rot<0>);
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integer sel_b = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(NOT(rot<0>));
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boolean sub_r = (rot<0> != rot<1>);
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boolean sub_i = (rot<1> == '1');</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="sqrdcmlah_z_zzzi_h, sqrdcmlah_z_zzzi_s" symboldefcount="1">
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<symbol link="sa_zda"><Zda></symbol>
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<account encodedin="Zda">
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<intro>
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<para>Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="sqrdcmlah_z_zzzi_h, sqrdcmlah_z_zzzi_s" symboldefcount="1">
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<symbol link="sa_zn"><Zn></symbol>
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<account encodedin="Zn">
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<intro>
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<para>Is the name of the first source scalable vector register, encoded in the "Zn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="sqrdcmlah_z_zzzi_h" symboldefcount="1">
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<symbol link="sa_zm"><Zm></symbol>
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<account encodedin="Zm">
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<docvars>
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<docvar key="as-structure-org" value="of-halfwords" />
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</docvars>
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<intro>
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<para>For the 16-bit variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="sqrdcmlah_z_zzzi_s" symboldefcount="2">
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<symbol link="sa_zm_1"><Zm></symbol>
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<account encodedin="Zm">
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<docvars>
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<docvar key="as-structure-org" value="of-words" />
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</docvars>
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<intro>
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<para>For the 32-bit variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="sqrdcmlah_z_zzzi_h" symboldefcount="1">
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<symbol link="sa_imm"><imm></symbol>
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<account encodedin="i2">
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<docvars>
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<docvar key="as-structure-org" value="of-halfwords" />
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</docvars>
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<intro>
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<para>For the 16-bit variant: is the element index, in the range 0 to 3, encoded in the "i2" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="sqrdcmlah_z_zzzi_s" symboldefcount="2">
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<symbol link="sa_imm_1"><imm></symbol>
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<account encodedin="i1">
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<docvars>
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<docvar key="as-structure-org" value="of-words" />
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</docvars>
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<intro>
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<para>For the 32-bit variant: is the element index, in the range 0 to 1, encoded in the "i1" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="sqrdcmlah_z_zzzi_h, sqrdcmlah_z_zzzi_s" symboldefcount="1">
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<symbol link="sa_const"><const></symbol>
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<definition encodedin="rot">
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<intro>Is the const specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">rot</entry>
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<entry class="symbol"><const></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="symbol">#0</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="symbol">#90</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="symbol">#180</entry>
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</row>
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<row>
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<entry class="bitfield">11</entry>
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<entry class="symbol">#270</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="SQRDCMLAH-Z.ZZZi-H" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
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constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
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constant integer PL = VL DIV 8;
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constant integer pairs = VL DIV (2 * esize);
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constant integer pairspersegment = 128 DIV (2 * esize);
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bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
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bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
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bits(VL) operand3 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[da, VL];
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bits(VL) result;
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integer round_const = 1 << (esize-1);
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integer res_r, res_i;
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for p = 0 to pairs-1
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integer segmentbase = p - (p MOD pairspersegment);
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integer s = segmentbase + index;
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integer elt1_a = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * p + sel_a, esize]);
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integer elt2_a = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * s + sel_a, esize]);
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integer elt2_b = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * s + sel_b, esize]);
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bits(esize) elt3_r = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, 2 * p + 0, esize];
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bits(esize) elt3_i = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, 2 * p + 1, esize];
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integer product_r = elt1_a * elt2_a;
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integer product_i = elt1_a * elt2_b;
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if sub_r then
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res_r = (<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(elt3_r) << esize) - 2 * product_r + round_const;
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else
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res_r = (<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(elt3_r) << esize) + 2 * product_r + round_const;
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if sub_i then
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res_i = (<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(elt3_i) << esize) - 2 * product_i + round_const;
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else
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res_i = (<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(elt3_i) << esize) + 2 * product_i + round_const;
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2 * p + 0, esize] = <a link="impl-aarch32.SignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) SignedSat(integer i, integer N)">SignedSat</a>(res_r >> esize, esize);
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2 * p + 1, esize] = <a link="impl-aarch32.SignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) SignedSat(integer i, integer N)">SignedSat</a>(res_i >> esize, esize);
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<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[da, VL] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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