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https://github.com/pound-emu/ballistic.git
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515 lines
23 KiB
XML
515 lines
23 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="SQRSHRN_advsimd" title="SQRSHRN, SQRSHRN2 -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SQRSHRN" />
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</docvars>
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<heading>SQRSHRN, SQRSHRN2</heading>
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<desc>
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<brief>
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<para>Signed saturating Rounded Shift Right Narrow (immediate)</para>
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</brief>
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<authored>
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<para>Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see <xref linkend="A64.instructions.SQSHRN_advsimd">SQSHRN</xref>.</para>
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<para>The <instruction>SQRSHRN</instruction> instruction writes the vector to the lower half of the destination register and clears the upper half, while the <instruction>SQRSHRN2</instruction> instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.</para>
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<para>If saturation occurs, the cumulative saturation bit <xref linkend="AArch64.fpsr">FPSR</xref>.QC is set.</para>
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<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from 2 classes:</txt>
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<a href="#iclass_sisd">Scalar</a>
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<txt> and </txt>
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<a href="#iclass_simd">Vector</a>
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</classesintro>
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<iclass name="Scalar" oneof="2" id="iclass_sisd" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-type" value="sisd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SQRSHRN" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/vector/shift/right-narrow/uniform/sisd" tworows="1">
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<box hibit="31" width="2" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="29" name="U" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="28" width="6" settings="6">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="22" width="4" name="immh" usename="1" settings="4" constraint="!= 0000" psbits="xxxx">
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<c colspan="4">!= 0000</c>
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</box>
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<box hibit="18" width="3" name="immb" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="15" width="4" name="opcode[4:1]" settings="4">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="11" name="op" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="10" settings="1">
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<c>1</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="SQRSHRN_asisdshf_N" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="advsimd-type" value="sisd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SQRSHRN" />
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</docvars>
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<asmtemplate><text>SQRSHRN </text><a link="sa_vb" hover="Destination width specifier (field "immh") [B,H,S]"><Vb></a><a link="sa_d" hover="SIMD&FP destination register number (field "Rd")"><d></a><text>, </text><a link="sa_va" hover="Source width specifier (field "immh") [D,H,S]"><Va></a><a link="sa_n" hover="First SIMD&FP source register number (field "Rn")"><n></a><text>, #</text><a link="sa_shift_1" hover="Right shift amount [1-the destination operand width in bits] (field "immh:immb")"><shift></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/shift/right-narrow/uniform/sisd" mylink="aarch64.instrs.vector.shift.right-narrow.uniform.sisd" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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if immh == '0000' then UNDEFINED;
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if immh<3> == '1' then UNDEFINED;
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integer esize = 8 << <a link="impl-shared.HighestSetBit.1" file="shared_pseudocode.xml" hover="function: integer HighestSetBit(bits(N) x)">HighestSetBit</a>(immh);
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integer datasize = esize;
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integer elements = 1;
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integer part = 0;
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integer shift = (2 * esize) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(immh:immb);
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boolean round = (op == '1');
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boolean unsigned = (U == '1');</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Vector" oneof="2" id="iclass_simd" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-type" value="simd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SQRSHRN" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/vector/shift/right-narrow/uniform/simd" tworows="1">
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<box hibit="31" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="29" name="U" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="28" width="6" settings="6">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="22" width="4" name="immh" usename="1" settings="4" constraint="!= 0000">
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<c colspan="4">!= 0000</c>
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</box>
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<box hibit="18" width="3" name="immb" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="15" width="4" name="opcode[4:1]" settings="4">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="11" name="op" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="10" settings="1">
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<c>1</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="SQRSHRN_asimdshf_N" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="advsimd-type" value="simd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SQRSHRN" />
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</docvars>
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<asmtemplate><text>SQRSHRN</text><a link="sa_2" hover="Second and upper half specifier (field "Q")">{2}</a><text> </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_tb" hover="Arrangement specifier (field "immh:Q") [2S,4H,4S,8B,8H,16B,SEE(asimdimm)]"><Tb></a><text>, </text><a link="sa_vn" hover="SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_ta" hover="Arrangement specifier (field "immh") [2D,4S,8H,SEE(asimdimm)]"><Ta></a><text>, #</text><a link="sa_shift" hover="Right shift amount [1-the destination element width in bits] (field "immh:immb")"><shift></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/shift/right-narrow/uniform/simd" mylink="aarch64.instrs.vector.shift.right-narrow.uniform.simd" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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if immh == '0000' then <a link="asimdimm" file="encodingindex.xml" hover="handled by an instruction in the 'Advanced SIMD modified immediate' class">SEE(asimdimm)</a>;
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if immh<3> == '1' then UNDEFINED;
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integer esize = 8 << <a link="impl-shared.HighestSetBit.1" file="shared_pseudocode.xml" hover="function: integer HighestSetBit(bits(N) x)">HighestSetBit</a>(immh);
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integer datasize = 64;
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integer part = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q);
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integer elements = datasize DIV esize;
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integer shift = (2 * esize) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(immh:immb);
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boolean round = (op == '1');
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boolean unsigned = (U == '1');</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="SQRSHRN_asimdshf_N" symboldefcount="1">
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<symbol link="sa_2">2</symbol>
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<definition encodedin="Q">
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<intro>Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">Q</entry>
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<entry class="symbol">2</entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">[absent]</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">[present]</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="SQRSHRN_asimdshf_N" symboldefcount="1">
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<symbol link="sa_vd"><Vd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="SQRSHRN_asimdshf_N" symboldefcount="1">
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<symbol link="sa_tb"><Tb></symbol>
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<definition encodedin="immh:Q">
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<intro>Is an arrangement specifier, </intro>
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<table class="valuetable">
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<tgroup cols="3">
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<thead>
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<row>
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<entry class="bitfield">immh</entry>
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<entry class="bitfield">Q</entry>
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<entry class="symbol"><Tb></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0000</entry>
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<entry class="bitfield">x</entry>
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<entry class="symbol" iclasslink="asimdimm" iclasslinkfile="encodingindex.xml">SEE Advanced SIMD modified immediate</entry>
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</row>
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<row>
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<entry class="bitfield">0001</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">8B</entry>
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</row>
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<row>
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<entry class="bitfield">0001</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">16B</entry>
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</row>
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<row>
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<entry class="bitfield">001x</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">4H</entry>
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</row>
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<row>
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<entry class="bitfield">001x</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">8H</entry>
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</row>
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<row>
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<entry class="bitfield">01xx</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">2S</entry>
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</row>
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<row>
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<entry class="bitfield">01xx</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">4S</entry>
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</row>
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<row>
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<entry class="bitfield">1xxx</entry>
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<entry class="bitfield">x</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="SQRSHRN_asimdshf_N" symboldefcount="1">
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<symbol link="sa_vn"><Vn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the name of the SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="SQRSHRN_asimdshf_N" symboldefcount="1">
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<symbol link="sa_ta"><Ta></symbol>
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<definition encodedin="immh">
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<intro>Is an arrangement specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">immh</entry>
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<entry class="symbol"><Ta></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0000</entry>
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<entry class="symbol" iclasslink="asimdimm" iclasslinkfile="encodingindex.xml">SEE Advanced SIMD modified immediate</entry>
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</row>
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<row>
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<entry class="bitfield">0001</entry>
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<entry class="symbol">8H</entry>
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</row>
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<row>
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<entry class="bitfield">001x</entry>
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<entry class="symbol">4S</entry>
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</row>
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<row>
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<entry class="bitfield">01xx</entry>
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<entry class="symbol">2D</entry>
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</row>
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<row>
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<entry class="bitfield">1xxx</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="SQRSHRN_asisdshf_N" symboldefcount="1">
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<symbol link="sa_vb"><Vb></symbol>
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<definition encodedin="immh">
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<intro>Is the destination width specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">immh</entry>
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<entry class="symbol"><Vb></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0000</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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<row>
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<entry class="bitfield">0001</entry>
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<entry class="symbol">B</entry>
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</row>
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<row>
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<entry class="bitfield">001x</entry>
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<entry class="symbol">H</entry>
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</row>
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<row>
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<entry class="bitfield">01xx</entry>
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<entry class="symbol">S</entry>
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</row>
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<row>
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<entry class="bitfield">1xxx</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="SQRSHRN_asisdshf_N" symboldefcount="1">
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<symbol link="sa_d"><d></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the number of the SIMD&FP destination register, in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="SQRSHRN_asisdshf_N" symboldefcount="1">
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<symbol link="sa_va"><Va></symbol>
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<definition encodedin="immh">
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<intro>Is the source width specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">immh</entry>
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<entry class="symbol"><Va></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0000</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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<row>
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<entry class="bitfield">0001</entry>
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|
<entry class="symbol">H</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">001x</entry>
|
|
<entry class="symbol">S</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01xx</entry>
|
|
<entry class="symbol">D</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1xxx</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="SQRSHRN_asisdshf_N" symboldefcount="1">
|
|
<symbol link="sa_n"><n></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the number of the first SIMD&FP source register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="SQRSHRN_asisdshf_N" symboldefcount="1">
|
|
<symbol link="sa_shift_1"><shift></symbol>
|
|
<definition encodedin="immh:immb">
|
|
<intro>For the scalar variant: is the right shift amount, in the range 1 to the destination operand width in bits, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">immh</entry>
|
|
<entry class="symbol"><shift></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0000</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0001</entry>
|
|
<entry class="symbol">(16-UInt(immh:immb))</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">001x</entry>
|
|
<entry class="symbol">(32-UInt(immh:immb))</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01xx</entry>
|
|
<entry class="symbol">(64-UInt(immh:immb))</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1xxx</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="SQRSHRN_asimdshf_N" symboldefcount="2">
|
|
<symbol link="sa_shift"><shift></symbol>
|
|
<definition encodedin="immh:immb">
|
|
<intro>For the vector variant: is the right shift amount, in the range 1 to the destination element width in bits, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">immh</entry>
|
|
<entry class="symbol"><shift></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0000</entry>
|
|
<entry class="symbol" iclasslink="asimdimm" iclasslinkfile="encodingindex.xml">SEE Advanced SIMD modified immediate</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0001</entry>
|
|
<entry class="symbol">(16-UInt(immh:immb))</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">001x</entry>
|
|
<entry class="symbol">(32-UInt(immh:immb))</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01xx</entry>
|
|
<entry class="symbol">(64-UInt(immh:immb))</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1xxx</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/vector/shift/right-narrow/uniform/sisd" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
|
|
bits(datasize*2) operand = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize*2];
|
|
bits(datasize) result;
|
|
integer round_const = if round then (1 << (shift - 1)) else 0;
|
|
integer element;
|
|
boolean sat;
|
|
|
|
for e = 0 to elements-1
|
|
element = (<a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 2*esize], unsigned) + round_const) >> shift;
|
|
(<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a link="impl-shared.SatQ.3" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
|
|
if sat then FPSR.QC = '1';
|
|
|
|
<a link="impl-aarch64.Vpart.write.3" file="shared_pseudocode.xml" hover="accessor: Vpart[integer n, integer part, integer width] = bits(width) value">Vpart</a>[d, part, datasize] = result;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|