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archived-ballistic/spec/arm64_xml/sqrshrn_z_mz4.xml
Ronald Caesar 26a677f8b4 decoder: Add ARM specification docs
Signed-off-by: Ronald Caesar <github43132@proton.me>
2025-12-12 18:11:36 -04:00

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<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<instructionsection id="sqrshrn_z_mz4" title="SQRSHRN" type="instruction">
<docvars>
<docvar key="instr-class" value="mortlach2" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="SQRSHRN" />
</docvars>
<heading>SQRSHRN</heading>
<desc>
<brief>Multi-vector signed saturating rounding shift right narrow by immediate and interleave</brief>
<description>
<para>Shift right by an immediate value, the signed integer value in each element of the four source vectors and place the four-way interleaved rounded results in the quarter-width destination elements. Each result element is saturated to the quarter-width N-bit element's signed integer range -2<sup>(N-1)</sup> to (2<sup>(N-1)</sup>)-1. The immediate shift amount is an unsigned value in the range 1 to number of bits per source element.</para>
<para>This instruction is unpredicated.</para>
</description>
<status>Green</status>
<predicated>False</predicated>
<sm_policy>SM_1_only</sm_policy>
</desc>
<alias_list howmany="0"></alias_list>
<classes>
<iclass name="SME2" oneof="1" id="iclass_mortlach2" no_encodings="1" isa="A64">
<docvars>
<docvar key="instr-class" value="mortlach2" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="SQRSHRN" />
</docvars>
<iclassintro count="1"></iclassintro>
<arch_variants>
<arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
</arch_variants>
<regdiagram form="32" psname="SQRSHRN-Z.MZ4-_" tworows="1">
<box hibit="31" width="8" settings="8">
<c>1</c>
<c>1</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>0</c>
<c>1</c>
</box>
<box hibit="23" width="2" name="tsize" usename="1">
<c colspan="2"></c>
</box>
<box hibit="21" settings="1">
<c>1</c>
</box>
<box hibit="20" width="5" name="imm5" usename="1">
<c colspan="5"></c>
</box>
<box hibit="15" width="5" settings="5">
<c>1</c>
<c>1</c>
<c>0</c>
<c>1</c>
<c>1</c>
</box>
<box hibit="10" name="N" usename="1" settings="1">
<c>1</c>
</box>
<box hibit="9" width="3" name="Zn" usename="1">
<c colspan="3"></c>
</box>
<box hibit="6" name="op" settings="1">
<c>0</c>
</box>
<box hibit="5" name="U" usename="1" settings="1">
<c>0</c>
</box>
<box hibit="4" width="5" name="Zd" usename="1">
<c colspan="5"></c>
</box>
</regdiagram>
<encoding name="sqrshrn_z_mz4_" oneofinclass="1" oneof="1" label="">
<docvars>
<docvar key="instr-class" value="mortlach2" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="SQRSHRN" />
</docvars>
<asmtemplate><text>SQRSHRN </text><a link="sa_zd" hover="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;tsize&quot;) [B,H]">&lt;T&gt;</a><text>, </text><text>{</text><text> </text><a link="sa_zn1" hover="First scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn1&gt;</a><text>.</text><a link="sa_tb" hover="Size specifier (field &quot;tsize&quot;) [D,S]">&lt;Tb&gt;</a><text>-</text><a link="sa_zn4" hover="Fourth scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn4&gt;</a><text>.</text><a link="sa_tb" hover="Size specifier (field &quot;tsize&quot;) [D,S]">&lt;Tb&gt;</a><text> </text><text>}</text><text>, #</text><a link="sa_const" hover="Immediate shift amount [1-number of bits per source element] (field &quot;tsize:imm5&quot;)">&lt;const&gt;</a></asmtemplate>
</encoding>
<ps_section howmany="1">
<ps name="SQRSHRN-Z.MZ4-_" mylink="SQRSHRN-Z.MZ4-_" enclabels="" sections="1" secttype="noheading">
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
integer esize;
case tsize of
when '00' UNDEFINED;
when '01' esize = 8;
when '1x' esize = 16;
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn:'00');
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);
integer shift = (8 * esize) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tsize:imm5);</pstext>
</ps>
</ps_section>
</iclass>
</classes>
<explanations scope="all">
<explanation enclist="sqrshrn_z_mz4_" symboldefcount="1">
<symbol link="sa_zd">&lt;Zd&gt;</symbol>
<account encodedin="Zd">
<intro>
<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="sqrshrn_z_mz4_" symboldefcount="1">
<symbol link="sa_t">&lt;T&gt;</symbol>
<definition encodedin="tsize">
<intro>Is the size specifier, </intro>
<table class="valuetable">
<tgroup cols="2">
<thead>
<row>
<entry class="bitfield">tsize</entry>
<entry class="symbol">&lt;T&gt;</entry>
</row>
</thead>
<tbody>
<row>
<entry class="bitfield">00</entry>
<entry class="symbol">RESERVED</entry>
</row>
<row>
<entry class="bitfield">01</entry>
<entry class="symbol">B</entry>
</row>
<row>
<entry class="bitfield">1x</entry>
<entry class="symbol">H</entry>
</row>
</tbody>
</tgroup>
</table>
</definition>
</explanation>
<explanation enclist="sqrshrn_z_mz4_" symboldefcount="1">
<symbol link="sa_zn1">&lt;Zn1&gt;</symbol>
<account encodedin="Zn">
<intro>
<para>Is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn" times 4.</para>
</intro>
</account>
</explanation>
<explanation enclist="sqrshrn_z_mz4_" symboldefcount="1">
<symbol link="sa_tb">&lt;Tb&gt;</symbol>
<definition encodedin="tsize">
<intro>Is the size specifier, </intro>
<table class="valuetable">
<tgroup cols="2">
<thead>
<row>
<entry class="bitfield">tsize</entry>
<entry class="symbol">&lt;Tb&gt;</entry>
</row>
</thead>
<tbody>
<row>
<entry class="bitfield">00</entry>
<entry class="symbol">RESERVED</entry>
</row>
<row>
<entry class="bitfield">01</entry>
<entry class="symbol">S</entry>
</row>
<row>
<entry class="bitfield">1x</entry>
<entry class="symbol">D</entry>
</row>
</tbody>
</tgroup>
</table>
</definition>
</explanation>
<explanation enclist="sqrshrn_z_mz4_" symboldefcount="1">
<symbol link="sa_zn4">&lt;Zn4&gt;</symbol>
<account encodedin="Zn">
<intro>
<para>Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zn" times 4 plus 3.</para>
</intro>
</account>
</explanation>
<explanation enclist="sqrshrn_z_mz4_" symboldefcount="1">
<symbol link="sa_const">&lt;const&gt;</symbol>
<account encodedin="imm5:tsize">
<intro>
<para>Is the immediate shift amount, in the range 1 to number of bits per source element, encoded in "tsize:imm5".</para>
</intro>
</account>
</explanation>
</explanations>
<ps_section howmany="1">
<ps name="SQRSHRN-Z.MZ4-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEEnabled()">CheckStreamingSVEEnabled</a>();
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
constant integer elements = VL DIV (4 * esize);
bits(VL) result;
integer round_const = 1 &lt;&lt; (shift-1);
for e = 0 to elements-1
for i = 0 to 3
bits(VL) operand = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n+i, VL];
bits(4 * esize) element = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 4 * esize];
integer res = (<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(element) + round_const) &gt;&gt; shift;
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 4*e + i, esize] = <a link="impl-aarch32.SignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) SignedSat(integer i, integer N)">SignedSat</a>(res, esize);
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</pstext>
</ps>
</ps_section>
</instructionsection>