archived-ballistic/spec/arm64_xml/ssbb_dsb.xml

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<instructionsection id="SSBB_DSB" title="SSBB -- A64" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="SSBB" />
    <docvar key="dsb-variants" value="dsb-memory" />
    <docvar key="instr-class" value="system" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="DSB" />
  </docvars>
  <heading>SSBB</heading>
  <desc>
    <brief>
      <para>Speculative Store Bypass Barrier</para>
    </brief>
    <authored>
      <para>Speculative Store Bypass Barrier is a memory barrier which prevents speculative loads from bypassing earlier stores to the same virtual address under certain conditions.</para>
      <para>The semantics of the Speculative Store Bypass Barrier are:</para>
      <list type="unordered">
        <listitem><content>When a load to a location appears in program order after the SSBB, then the load does not speculatively read an entry earlier in the coherence order for that location than the entry generated by the latest store satisfying all of the following conditions:<list type="unordered"><listitem><content>The store is to the same location as the load.</content></listitem><listitem><content>The store uses the same virtual address as the load.</content></listitem><listitem><content>The store appears in program order before the SSBB.</content></listitem></list></content></listitem>
        <listitem><content>When a load to a location appears in program order before the SSBB, then the load does not speculatively read data from any store satisfying all of the following conditions:<list type="unordered"><listitem><content>The store is to the same location as the load.</content></listitem><listitem><content>The store uses the same virtual address as the load.</content></listitem><listitem><content>The store appears in program order after the SSBB.</content></listitem></list></content></listitem>
      </list>
    </authored>
  </desc>
  <aliasto refiform="dsb.xml" iformid="DSB">DSB</aliasto>
  <classes>
    <iclass name="Memory barrier" oneof="1" id="iclass_dsb_memory" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="dsb-variants" value="dsb-memory" />
        <docvar key="instr-class" value="system" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="DSB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/system/barriers/dsb" tworows="1">
        <box hibit="31" width="10" settings="10">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" width="2" name="op0" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="CRn" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="CRm" usename="1" settings="4" psbits="xxxx">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="op2[2]" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="opc" usename="1" settings="2" psbits="xx">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" width="5" name="Rt" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="SSBB_DSB_BO_barriers" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="alias_mnemonic" value="SSBB" />
          <docvar key="dsb-variants" value="dsb-memory" />
          <docvar key="instr-class" value="system" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="DSB" />
        </docvars>
        <asmtemplate><text>SSBB</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="dsb.xml#DSB_BO_barriers">DSB</a><text> #0</text></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all"></explanations>
</instructionsection>