mirror of
https://github.com/pound-emu/ballistic.git
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570 lines
33 KiB
XML
570 lines
33 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="st1w_z_p_bz" title="ST1W (scalar plus vector)" type="instruction">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ST1W" />
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</docvars>
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<heading>ST1W (scalar plus vector)</heading>
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<desc>
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<brief>Scatter store words from a vector (vector index)</brief>
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<description>
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<para>Scatter store of words from the active elements of a vector register to the memory addresses generated by a 64-bit scalar base plus vector index. The index values are optionally first sign or zero-extended from 32 to 64 bits and then optionally multiplied by 4. Inactive elements are not written to memory.</para>
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<para>This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.</para>
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</description>
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<status>Green</status>
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<predicated>True</predicated>
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<sm_policy>SM_0_only</sm_policy>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="6">
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<txt>It has encodings from 6 classes:</txt>
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<a href="#iclass_off_s_x32_scaled">32-bit scaled offset</a>
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<txt>, </txt>
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<a href="#iclass_off_d_x32_scaled">32-bit unpacked scaled offset</a>
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<txt>, </txt>
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<a href="#iclass_off_d_x32_unscaled">32-bit unpacked unscaled offset</a>
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<txt>, </txt>
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<a href="#iclass_off_s_x32_unscaled">32-bit unscaled offset</a>
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<txt>, </txt>
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<a href="#iclass_off_d_64_scaled">64-bit scaled offset</a>
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<txt> and </txt>
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<a href="#iclass_off_d_64_unscaled">64-bit unscaled offset</a>
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</classesintro>
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<iclass name="32-bit scaled offset" oneof="6" id="iclass_off_s_x32_scaled" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ST1W" />
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<docvar key="sve-offset-type" value="off_s_x32_scaled" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="ST1W-Z.P.BZ-S.x32.scaled" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" name="msz<1>" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="23" name="msz<0>" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" width="2" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Zm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" settings="1">
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<c>1</c>
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</box>
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<box hibit="14" name="xs" usename="1">
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<c></c>
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</box>
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<box hibit="13" settings="1">
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<c>0</c>
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</box>
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<box hibit="12" width="3" name="Pg" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="st1w_z_p_bz_s_x32_scaled" oneofinclass="1" oneof="6" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ST1W" />
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<docvar key="sve-offset-type" value="off_s_x32_scaled" />
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</docvars>
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<asmtemplate><text>ST1W </text><text>{</text><text> </text><a link="sa_zt" hover="Scalable vector register to be transferred (field "Zt")"><Zt></a><text>.S </text><text>}</text><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>, </text><a link="sa_zm" hover="Offset scalable vector register (field "Zm")"><Zm></a><text>.S, </text><a link="sa_mod" hover="Index extend and shift specifier (field "xs") [SXTW,UXTW]"><mod></a><text> #2]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="ST1W-Z.P.BZ-S.x32.scaled" mylink="ST1W-Z.P.BZ-S.x32.scaled" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zt);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
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integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
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constant integer esize = 32;
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constant integer msize = 32;
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integer offs_size = 32;
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boolean offs_unsigned = xs == '0';
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integer scale = 2;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="32-bit unpacked scaled offset" oneof="6" id="iclass_off_d_x32_scaled" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ST1W" />
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<docvar key="sve-offset-type" value="off_d_x32_scaled" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="ST1W-Z.P.BZ-D.x32.scaled" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" name="msz<1>" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="23" name="msz<0>" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" width="2" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Zm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" settings="1">
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<c>1</c>
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</box>
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<box hibit="14" name="xs" usename="1">
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<c></c>
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</box>
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<box hibit="13" settings="1">
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<c>0</c>
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</box>
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<box hibit="12" width="3" name="Pg" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="st1w_z_p_bz_d_x32_scaled" oneofinclass="1" oneof="6" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ST1W" />
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<docvar key="sve-offset-type" value="off_d_x32_scaled" />
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</docvars>
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<asmtemplate><text>ST1W </text><text>{</text><text> </text><a link="sa_zt" hover="Scalable vector register to be transferred (field "Zt")"><Zt></a><text>.D </text><text>}</text><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>, </text><a link="sa_zm" hover="Offset scalable vector register (field "Zm")"><Zm></a><text>.D, </text><a link="sa_mod" hover="Index extend and shift specifier (field "xs") [SXTW,UXTW]"><mod></a><text> #2]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="ST1W-Z.P.BZ-D.x32.scaled" mylink="ST1W-Z.P.BZ-D.x32.scaled" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zt);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
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integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
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constant integer esize = 64;
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constant integer msize = 32;
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integer offs_size = 32;
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boolean offs_unsigned = xs == '0';
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integer scale = 2;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="32-bit unpacked unscaled offset" oneof="6" id="iclass_off_d_x32_unscaled" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ST1W" />
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<docvar key="sve-offset-type" value="off_d_x32_unscaled" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="ST1W-Z.P.BZ-D.x32.unscaled" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" name="msz<1>" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="23" name="msz<0>" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" width="2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="20" width="5" name="Zm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" settings="1">
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<c>1</c>
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</box>
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<box hibit="14" name="xs" usename="1">
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<c></c>
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</box>
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<box hibit="13" settings="1">
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<c>0</c>
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</box>
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<box hibit="12" width="3" name="Pg" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="st1w_z_p_bz_d_x32_unscaled" oneofinclass="1" oneof="6" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ST1W" />
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<docvar key="sve-offset-type" value="off_d_x32_unscaled" />
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</docvars>
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<asmtemplate><text>ST1W </text><text>{</text><text> </text><a link="sa_zt" hover="Scalable vector register to be transferred (field "Zt")"><Zt></a><text>.D </text><text>}</text><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>, </text><a link="sa_zm" hover="Offset scalable vector register (field "Zm")"><Zm></a><text>.D, </text><a link="sa_mod" hover="Index extend and shift specifier (field "xs") [SXTW,UXTW]"><mod></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="ST1W-Z.P.BZ-D.x32.unscaled" mylink="ST1W-Z.P.BZ-D.x32.unscaled" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zt);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
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integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
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constant integer esize = 64;
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constant integer msize = 32;
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integer offs_size = 32;
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boolean offs_unsigned = xs == '0';
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integer scale = 0;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="32-bit unscaled offset" oneof="6" id="iclass_off_s_x32_unscaled" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ST1W" />
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<docvar key="sve-offset-type" value="off_s_x32_unscaled" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="ST1W-Z.P.BZ-S.x32.unscaled" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" name="msz<1>" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="23" name="msz<0>" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="20" width="5" name="Zm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" settings="1">
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<c>1</c>
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</box>
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<box hibit="14" name="xs" usename="1">
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<c></c>
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</box>
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<box hibit="13" settings="1">
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<c>0</c>
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</box>
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<box hibit="12" width="3" name="Pg" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="st1w_z_p_bz_s_x32_unscaled" oneofinclass="1" oneof="6" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ST1W" />
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<docvar key="sve-offset-type" value="off_s_x32_unscaled" />
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</docvars>
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<asmtemplate><text>ST1W </text><text>{</text><text> </text><a link="sa_zt" hover="Scalable vector register to be transferred (field "Zt")"><Zt></a><text>.S </text><text>}</text><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>, </text><a link="sa_zm" hover="Offset scalable vector register (field "Zm")"><Zm></a><text>.S, </text><a link="sa_mod" hover="Index extend and shift specifier (field "xs") [SXTW,UXTW]"><mod></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="ST1W-Z.P.BZ-S.x32.unscaled" mylink="ST1W-Z.P.BZ-S.x32.unscaled" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zt);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
|
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
|
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
|
constant integer esize = 32;
|
|
constant integer msize = 32;
|
|
integer offs_size = 32;
|
|
boolean offs_unsigned = xs == '0';
|
|
integer scale = 0;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="64-bit scaled offset" oneof="6" id="iclass_off_d_64_scaled" no_encodings="1" isa="A64">
|
|
<docvars>
|
|
<docvar key="instr-class" value="sve" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="ST1W" />
|
|
<docvar key="sve-offset-type" value="off_d_64_scaled" />
|
|
</docvars>
|
|
<iclassintro count="1"></iclassintro>
|
|
<regdiagram form="32" psname="ST1W-Z.P.BZ-D.64.scaled" tworows="1">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" name="msz<1>" usename="1" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="msz<0>" usename="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="st1w_z_p_bz_d_64_scaled" oneofinclass="1" oneof="6" label="">
|
|
<docvars>
|
|
<docvar key="instr-class" value="sve" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="ST1W" />
|
|
<docvar key="sve-offset-type" value="off_d_64_scaled" />
|
|
</docvars>
|
|
<asmtemplate><text>ST1W </text><text>{</text><text> </text><a link="sa_zt" hover="Scalable vector register to be transferred (field "Zt")"><Zt></a><text>.D </text><text>}</text><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>, </text><a link="sa_zm" hover="Offset scalable vector register (field "Zm")"><Zm></a><text>.D, LSL #2]</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="ST1W-Z.P.BZ-D.64.scaled" mylink="ST1W-Z.P.BZ-D.64.scaled" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
|
|
integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zt);
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
|
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
|
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
|
constant integer esize = 64;
|
|
constant integer msize = 32;
|
|
integer offs_size = 64;
|
|
boolean offs_unsigned = TRUE;
|
|
integer scale = 2;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="64-bit unscaled offset" oneof="6" id="iclass_off_d_64_unscaled" no_encodings="1" isa="A64">
|
|
<docvars>
|
|
<docvar key="instr-class" value="sve" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="ST1W" />
|
|
<docvar key="sve-offset-type" value="off_d_64_unscaled" />
|
|
</docvars>
|
|
<iclassintro count="1"></iclassintro>
|
|
<regdiagram form="32" psname="ST1W-Z.P.BZ-D.64.unscaled" tworows="1">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" name="msz<1>" usename="1" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="msz<0>" usename="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="st1w_z_p_bz_d_64_unscaled" oneofinclass="1" oneof="6" label="">
|
|
<docvars>
|
|
<docvar key="instr-class" value="sve" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="ST1W" />
|
|
<docvar key="sve-offset-type" value="off_d_64_unscaled" />
|
|
</docvars>
|
|
<asmtemplate><text>ST1W </text><text>{</text><text> </text><a link="sa_zt" hover="Scalable vector register to be transferred (field "Zt")"><Zt></a><text>.D </text><text>}</text><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>, </text><a link="sa_zm" hover="Offset scalable vector register (field "Zm")"><Zm></a><text>.D]</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="ST1W-Z.P.BZ-D.64.unscaled" mylink="ST1W-Z.P.BZ-D.64.unscaled" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
|
|
integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zt);
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
|
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
|
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
|
constant integer esize = 64;
|
|
constant integer msize = 32;
|
|
integer offs_size = 64;
|
|
boolean offs_unsigned = TRUE;
|
|
integer scale = 0;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="st1w_z_p_bz_d_64_scaled, st1w_z_p_bz_d_64_unscaled, st1w_z_p_bz_d_x32_scaled, st1w_z_p_bz_d_x32_unscaled, st1w_z_p_bz_s_x32_scaled, st1w_z_p_bz_s_x32_unscaled" symboldefcount="1">
|
|
<symbol link="sa_zt"><Zt></symbol>
|
|
<account encodedin="Zt">
|
|
<intro>
|
|
<para>Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="st1w_z_p_bz_d_64_scaled, st1w_z_p_bz_d_64_unscaled, st1w_z_p_bz_d_x32_scaled, st1w_z_p_bz_d_x32_unscaled, st1w_z_p_bz_s_x32_scaled, st1w_z_p_bz_s_x32_unscaled" symboldefcount="1">
|
|
<symbol link="sa_pg"><Pg></symbol>
|
|
<account encodedin="Pg">
|
|
<intro>
|
|
<para>Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="st1w_z_p_bz_d_64_scaled, st1w_z_p_bz_d_64_unscaled, st1w_z_p_bz_d_x32_scaled, st1w_z_p_bz_d_x32_unscaled, st1w_z_p_bz_s_x32_scaled, st1w_z_p_bz_s_x32_unscaled" symboldefcount="1">
|
|
<symbol link="sa_xn_sp"><Xn|SP></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="st1w_z_p_bz_d_64_scaled, st1w_z_p_bz_d_64_unscaled, st1w_z_p_bz_d_x32_scaled, st1w_z_p_bz_d_x32_unscaled, st1w_z_p_bz_s_x32_scaled, st1w_z_p_bz_s_x32_unscaled" symboldefcount="1">
|
|
<symbol link="sa_zm"><Zm></symbol>
|
|
<account encodedin="Zm">
|
|
<intro>
|
|
<para>Is the name of the offset scalable vector register, encoded in the "Zm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="st1w_z_p_bz_d_x32_scaled, st1w_z_p_bz_d_x32_unscaled, st1w_z_p_bz_s_x32_scaled, st1w_z_p_bz_s_x32_unscaled" symboldefcount="1">
|
|
<symbol link="sa_mod"><mod></symbol>
|
|
<definition encodedin="xs">
|
|
<intro>Is the index extend and shift specifier, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">xs</entry>
|
|
<entry class="symbol"><mod></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">UXTW</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">SXTW</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="ST1W-Z.P.BZ-S.x32.scaled" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckNonStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
|
|
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
|
constant integer PL = VL DIV 8;
|
|
constant integer elements = VL DIV esize;
|
|
bits(64) base;
|
|
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
|
bits(VL) offset;
|
|
bits(VL) src;
|
|
constant integer mbytes = msize DIV 8;
|
|
boolean contiguous = FALSE;
|
|
boolean nontemporal = FALSE;
|
|
boolean tagchecked = TRUE;
|
|
<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescSVE.4" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescSVE(MemOp memop, boolean nontemporal, boolean contiguous, boolean tagchecked)">CreateAccDescSVE</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>, nontemporal, contiguous, tagchecked);
|
|
|
|
if !<a link="impl-aarch64.AnyActiveElement.2" file="shared_pseudocode.xml" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then
|
|
if n == 31 && <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_CHECKSPNONEACTIVE" file="shared_pseudocode.xml" hover="enumeration Unpredictable { Unpredictable_VMSR, Unpredictable_WBOVERLAPLD, Unpredictable_WBOVERLAPST, Unpredictable_LDPOVERLAP, Unpredictable_BASEOVERLAP, Unpredictable_DATAOVERLAP, Unpredictable_DEVPAGE2, Unpredictable_INSTRDEVICE, Unpredictable_RESCPACR, Unpredictable_RESMAIR, Unpredictable_S1CTAGGED, Unpredictable_S2RESMEMATTR, Unpredictable_RESTEXCB, Unpredictable_RESPRRR, Unpredictable_RESDACR, Unpredictable_RESVTCRS, Unpredictable_RESTnSZ, Unpredictable_RESTCF, Unpredictable_DEVICETAGSTORE, Unpredictable_OORTnSZ, Unpredictable_LARGEIPA, Unpredictable_ESRCONDPASS, Unpredictable_ILZEROIT, Unpredictable_ILZEROT, Unpredictable_BPVECTORCATCHPRI, Unpredictable_VCMATCHHALF, Unpredictable_VCMATCHDAPA, Unpredictable_WPMASKANDBAS, Unpredictable_WPBASCONTIGUOUS, Unpredictable_RESWPMASK, Unpredictable_WPMASKEDBITS, Unpredictable_RESBPWPCTRL, Unpredictable_BPNOTIMPL, Unpredictable_RESBPTYPE, Unpredictable_BPNOTCTXCMP, Unpredictable_BPMATCHHALF, Unpredictable_BPMISMATCHHALF, Unpredictable_RESTARTALIGNPC, Unpredictable_RESTARTZEROUPPERPC, Unpredictable_ZEROUPPER, Unpredictable_ERETZEROUPPERPC, Unpredictable_A32FORCEALIGNPC, Unpredictable_SMD, Unpredictable_NONFAULT, Unpredictable_SVEZEROUPPER, Unpredictable_SVELDNFDATA, Unpredictable_SVELDNFZERO, Unpredictable_CHECKSPNONEACTIVE, Unpredictable_SMEZEROUPPER, Unpredictable_NVNV1, Unpredictable_Shareability, Unpredictable_AFUPDATE, Unpredictable_DBUPDATE, Unpredictable_IESBinDebug, Unpredictable_BADPMSFCR, Unpredictable_ZEROBTYPE, Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP, Unpredictable_RESERVEDNSxB, Unpredictable_WFxTDEBUG, Unpredictable_LS64UNSUPPORTED, Unpredictable_MISALIGNEDATOMIC, Unpredictable_CLEARERRITEZERO, Unpredictable_ALUEXCEPTIONRETURN, Unpredictable_IGNORETRAPINDEBUG, Unpredictable_DBGxVR_RESS, Unpredictable_PMUEVENTCOUNTER, Unpredictable_PMSCR_PCT, Unpredictable_CounterReservedForEL2, Unpredictable_BRBFILTRATE, Unpredictable_MOPSOVERLAP31, Unpredictable_STOREONLYTAGCHECKEDCAS, Unpredictable_RESTC }">Unpredictable_CHECKSPNONEACTIVE</a>) then
|
|
<a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
|
|
else
|
|
if n == 31 then <a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
|
|
base = if n == 31 then <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[] else <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
|
|
offset = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
|
src = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[t, VL];
|
|
|
|
for e = 0 to elements-1
|
|
if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
|
integer off = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[offset, e, esize]<offs_size-1:0>, offs_unsigned);
|
|
bits(64) addr = base + (off << scale);
|
|
Mem[addr, mbytes, accdesc] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[src, e, esize]<msize-1:0>;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|