mirror of
https://github.com/pound-emu/ballistic.git
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147 lines
7.2 KiB
XML
147 lines
7.2 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="STCLRH_LDCLRH" title="STCLRH, STCLRLH -- A64" type="alias">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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</docvars>
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<heading>STCLRH, STCLRLH</heading>
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<desc>
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<brief>
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<para>Atomic bit clear on halfword in memory, without return</para>
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</brief>
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<authored>
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<para>Atomic bit clear on halfword in memory, without return, atomically loads a 16-bit halfword from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory.</para>
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<list type="unordered">
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<listitem><content><instruction>STCLRH</instruction> does not have release semantics.</content></listitem>
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<listitem><content><instruction>STCLRLH</instruction> stores to memory with release semantics, as described in <xref linkend="BEIHCHEF">Load-Acquire, Store-Release</xref>.</content></listitem>
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</list>
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<para>For information about memory accesses see <xref linkend="CHDIIIBB">Load/Store addressing modes</xref>.</para>
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</authored>
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</desc>
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<operationalnotes>
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<para>If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
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</operationalnotes>
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<aliasto refiform="ldclrh.xml" iformid="LDCLRH">LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH</aliasto>
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<classes>
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<iclass name="Integer" oneof="1" id="iclass_general" no_encodings="2" isa="A64">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.1" feature="FEAT_LSE" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/memory/atomicops/ld" tworows="1">
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<box hibit="31" width="2" name="size" usename="1" settings="2" psbits="xx">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="29" width="3" settings="3">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="26" name="V" settings="1">
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<c>0</c>
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</box>
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<box hibit="25" width="2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" name="A" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="22" name="R" usename="1">
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<c></c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Rs" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" name="o3" settings="1">
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<c>0</c>
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</box>
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<box hibit="14" width="3" name="opc" usename="1" settings="3" psbits="xxx">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rt" usename="1" settings="5" psbits="xxxxx">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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</regdiagram>
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<encoding name="STCLRH_LDCLRH_32_memop" oneofinclass="2" oneof="2" label="No memory ordering" bitdiffs="R == 0">
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<docvars>
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<docvar key="alias_mnemonic" value="STCLRH" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="loadstore-order" value="no-order" />
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<docvar key="mnemonic" value="LDCLRH" />
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</docvars>
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<box hibit="22" width="1" name="R">
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<c>0</c>
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</box>
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<asmtemplate><text>STCLRH </text><a link="sa_ws" hover="32-bit general-purpose register holding data value to be operated on with the contents of memory location (field "Rs")"><Ws></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>]</text></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="ldclrh.xml#LDCLRH_32_memop">LDCLRH</a><text> </text><a link="sa_ws" hover="32-bit general-purpose register holding data value to be operated on with the contents of memory location (field "Rs")"><Ws></a><text>, WZR, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>]</text></asmtemplate>
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<aliascond>Unconditionally</aliascond>
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</equivalent_to>
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</encoding>
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<encoding name="STCLRLH_LDCLRLH_32_memop" oneofinclass="2" oneof="2" label="Release" bitdiffs="R == 1">
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<docvars>
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<docvar key="alias_mnemonic" value="STCLRLH" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="loadstore-order" value="release" />
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<docvar key="mnemonic" value="LDCLRLH" />
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</docvars>
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<box hibit="22" width="1" name="R">
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<c>1</c>
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</box>
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<asmtemplate><text>STCLRLH </text><a link="sa_ws" hover="32-bit general-purpose register holding data value to be operated on with the contents of memory location (field "Rs")"><Ws></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>]</text></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="ldclrh.xml#LDCLRLH_32_memop">LDCLRLH</a><text> </text><a link="sa_ws" hover="32-bit general-purpose register holding data value to be operated on with the contents of memory location (field "Rs")"><Ws></a><text>, WZR, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>]</text></asmtemplate>
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<aliascond>Unconditionally</aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="STCLRH_LDCLRH_32_memop" symboldefcount="1">
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<symbol link="sa_ws"><Ws></symbol>
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<account encodedin="Rs">
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<intro>
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<para>Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="STCLRH_LDCLRH_32_memop" symboldefcount="1">
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<symbol link="sa_xn_sp"><Xn|SP></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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</instructionsection>
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