mirror of
https://github.com/pound-emu/ballistic.git
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350 lines
20 KiB
XML
350 lines
20 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="STGP" title="STGP -- A64" type="instruction">
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<docvars>
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<docvar key="atomic-ops" value="STGP-pair-64" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STGP" />
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<docvar key="offset-type" value="off7s_s" />
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<docvar key="reg-type" value="pair-64" />
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</docvars>
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<heading>STGP</heading>
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<desc>
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<brief>
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<para>Store Allocation Tag and Pair of registers</para>
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</brief>
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<authored>
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<para>Store Allocation Tag and Pair of registers stores an Allocation Tag and two 64-bit doublewords to memory, from two registers. The address used for the store is calculated from the base register and an immediate signed offset scaled by the Tag granule. The Allocation Tag is calculated from the Logical Address Tag in the base register.</para>
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<para>This instruction generates an Unchecked access.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="3">
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<txt>It has encodings from 3 classes:</txt>
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<a href="#iclass_post_indexed">Post-index</a>
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<txt>, </txt>
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<a href="#iclass_pre_indexed">Pre-index</a>
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<txt> and </txt>
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<a href="#iclass_signed_scaled_offset">Signed offset</a>
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</classesintro>
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<iclass name="Post-index" oneof="3" id="iclass_post_indexed" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="address-form" value="post-indexed" />
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<docvar key="address-form-reg-type" value="post-indexed-pair-64" />
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<docvar key="atomic-ops" value="STGP-pair-64" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STGP" />
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<docvar key="offset-type" value="off7s_s" />
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<docvar key="reg-type" value="pair-64" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.5" feature="FEAT_MTE" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/integer/tags/mcsettaganddatapairpost">
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<box hibit="31" name="opc<1>" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="opc<0>" settings="1">
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<c>1</c>
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</box>
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<box hibit="29" width="3" settings="3">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="26" name="V" settings="1">
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<c>0</c>
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</box>
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<box hibit="25" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="22" name="L" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" width="7" name="simm7" usename="1">
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<c colspan="7"></c>
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</box>
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<box hibit="14" width="5" name="Xt2" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="9" width="5" name="Xn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Xt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="STGP_64_ldstpair_post" oneofinclass="1" oneof="3" label="">
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<docvars>
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<docvar key="address-form" value="post-indexed" />
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<docvar key="address-form-reg-type" value="post-indexed-pair-64" />
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<docvar key="atomic-ops" value="STGP-pair-64" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STGP" />
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<docvar key="offset-type" value="off7s_s" />
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<docvar key="reg-type" value="pair-64" />
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</docvars>
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<asmtemplate><text>STGP </text><a link="sa_xt1" hover="First 64-bit general-purpose register to be transferred (field "Xt")"><Xt1></a><text>, </text><a link="sa_xt2" hover="Second 64-bit general-purpose register to be transferred (field "Xt2")"><Xt2></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Xn")"><Xn|SP></a><text>], #</text><a link="sa_imm_1" hover="Signed immediate offset, multiple of 16 [-1024-1008] (field "simm7")"><imm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/integer/tags/mcsettaganddatapairpost" mylink="aarch64.instrs.integer.tags.mcsettaganddatapairpost" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveMTEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEExt()">HaveMTEExt</a>() then UNDEFINED;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xn);
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt);
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integer t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt2);
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bits(64) offset = <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(simm7, 64), <a link="LOG2_TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer LOG2_TAG_GRANULE = 4">LOG2_TAG_GRANULE</a>);
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boolean writeback = TRUE;
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boolean postindex = TRUE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Pre-index" oneof="3" id="iclass_pre_indexed" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="address-form" value="pre-indexed" />
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<docvar key="address-form-reg-type" value="pre-indexed-pair-64" />
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<docvar key="atomic-ops" value="STGP-pair-64" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STGP" />
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<docvar key="offset-type" value="off7s_s" />
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<docvar key="reg-type" value="pair-64" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.5" feature="FEAT_MTE" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/integer/tags/mcsettaganddatapairpre">
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<box hibit="31" name="opc<1>" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="opc<0>" settings="1">
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<c>1</c>
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</box>
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<box hibit="29" width="3" settings="3">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="26" name="V" settings="1">
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<c>0</c>
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</box>
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<box hibit="25" width="3" settings="3">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="22" name="L" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" width="7" name="simm7" usename="1">
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<c colspan="7"></c>
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</box>
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<box hibit="14" width="5" name="Xt2" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="9" width="5" name="Xn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Xt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="STGP_64_ldstpair_pre" oneofinclass="1" oneof="3" label="">
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<docvars>
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<docvar key="address-form" value="pre-indexed" />
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<docvar key="address-form-reg-type" value="pre-indexed-pair-64" />
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<docvar key="atomic-ops" value="STGP-pair-64" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STGP" />
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<docvar key="offset-type" value="off7s_s" />
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<docvar key="reg-type" value="pair-64" />
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</docvars>
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<asmtemplate><text>STGP </text><a link="sa_xt1" hover="First 64-bit general-purpose register to be transferred (field "Xt")"><Xt1></a><text>, </text><a link="sa_xt2" hover="Second 64-bit general-purpose register to be transferred (field "Xt2")"><Xt2></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Xn")"><Xn|SP></a><text>, #</text><a link="sa_imm_1" hover="Signed immediate offset, multiple of 16 [-1024-1008] (field "simm7")"><imm></a><text>]!</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/integer/tags/mcsettaganddatapairpre" mylink="aarch64.instrs.integer.tags.mcsettaganddatapairpre" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveMTEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEExt()">HaveMTEExt</a>() then UNDEFINED;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xn);
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt);
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integer t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt2);
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bits(64) offset = <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(simm7, 64), <a link="LOG2_TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer LOG2_TAG_GRANULE = 4">LOG2_TAG_GRANULE</a>);
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boolean writeback = TRUE;
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boolean postindex = FALSE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Signed offset" oneof="3" id="iclass_signed_scaled_offset" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="address-form" value="signed-scaled-offset" />
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<docvar key="address-form-reg-type" value="signed-scaled-offset-pair-64" />
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<docvar key="atomic-ops" value="STGP-pair-64" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STGP" />
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<docvar key="offset-type" value="off7s_s" />
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<docvar key="reg-type" value="pair-64" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.5" feature="FEAT_MTE" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/integer/tags/mcsettaganddatapair">
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<box hibit="31" name="opc<1>" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="opc<0>" settings="1">
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<c>1</c>
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</box>
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<box hibit="29" width="3" settings="3">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="26" name="V" settings="1">
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<c>0</c>
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</box>
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<box hibit="25" width="3" settings="3">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="22" name="L" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" width="7" name="simm7" usename="1">
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<c colspan="7"></c>
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</box>
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<box hibit="14" width="5" name="Xt2" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="9" width="5" name="Xn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Xt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="STGP_64_ldstpair_off" oneofinclass="1" oneof="3" label="">
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<docvars>
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<docvar key="address-form" value="signed-scaled-offset" />
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<docvar key="address-form-reg-type" value="signed-scaled-offset-pair-64" />
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<docvar key="atomic-ops" value="STGP-pair-64" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STGP" />
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<docvar key="offset-type" value="off7s_s" />
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<docvar key="reg-type" value="pair-64" />
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</docvars>
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<asmtemplate><text>STGP </text><a link="sa_xt1" hover="First 64-bit general-purpose register to be transferred (field "Xt")"><Xt1></a><text>, </text><a link="sa_xt2" hover="Second 64-bit general-purpose register to be transferred (field "Xt2")"><Xt2></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Xn")"><Xn|SP></a><text>{</text><text>, #</text><a link="sa_imm" hover="Optional signed immediate offset, multiple of 16 [-1024-1008], default 0 (field "simm7")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/integer/tags/mcsettaganddatapair" mylink="aarch64.instrs.integer.tags.mcsettaganddatapair" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveMTEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEExt()">HaveMTEExt</a>() then UNDEFINED;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xn);
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt);
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integer t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt2);
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bits(64) offset = <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(simm7, 64), <a link="LOG2_TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer LOG2_TAG_GRANULE = 4">LOG2_TAG_GRANULE</a>);
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boolean writeback = FALSE;
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boolean postindex = FALSE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="STGP_64_ldstpair_off, STGP_64_ldstpair_post, STGP_64_ldstpair_pre" symboldefcount="1">
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<symbol link="sa_xt1"><Xt1></symbol>
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<account encodedin="Xt">
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<intro>
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<para>Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Xt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="STGP_64_ldstpair_off, STGP_64_ldstpair_post, STGP_64_ldstpair_pre" symboldefcount="1">
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<symbol link="sa_xt2"><Xt2></symbol>
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<account encodedin="Xt2">
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<intro>
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<para>Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Xt2" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="STGP_64_ldstpair_off, STGP_64_ldstpair_post, STGP_64_ldstpair_pre" symboldefcount="1">
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<symbol link="sa_xn_sp"><Xn|SP></symbol>
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<account encodedin="Xn">
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<intro>
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<para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Xn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="STGP_64_ldstpair_post, STGP_64_ldstpair_pre" symboldefcount="1">
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<symbol link="sa_imm_1"><imm></symbol>
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<account encodedin="simm7">
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<intro>
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<para>For the post-index and pre-index variant: is the signed immediate offset, a multiple of 16 in the range -1024 to 1008, encoded in the "simm7" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="STGP_64_ldstpair_off" symboldefcount="2">
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<symbol link="sa_imm"><imm></symbol>
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<account encodedin="simm7">
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<docvars>
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<docvar key="address-form" value="signed-scaled-offset" />
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<docvar key="address-form-reg-type" value="signed-scaled-offset-pair-64" />
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</docvars>
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<intro>
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<para>For the signed offset variant: is the optional signed immediate offset, a multiple of 16 in the range -1024 to 1008, defaulting to 0 and encoded in the "simm7" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/integer/tags/mcsettaganddatapairpost" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(64) address;
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bits(64) data1;
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bits(64) data2;
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if n == 31 then
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<a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
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address = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
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else
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address = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
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data1 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[t, 64];
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data2 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[t2, 64];
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if !postindex then
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address = address + offset;
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<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescLDGSTG.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescLDGSTG(MemOp memop)">CreateAccDescLDGSTG</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>);
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if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, <a link="TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer TAG_GRANULE = 1 << LOG2_TAG_GRANULE">TAG_GRANULE</a>) then
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<a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));
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Mem[address, 8, accdesc] = data1;
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Mem[address+8, 8, accdesc] = data2;
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<a link="AArch64.MemTag.write.2" file="shared_pseudocode.xml" hover="accessor: AArch64.MemTag[bits(64) address, AccessDescriptor accdesc_in] = bits(4) value">AArch64.MemTag</a>[address, accdesc] = <a link="AArch64.AllocationTagFromAddress.1" file="shared_pseudocode.xml" hover="function: bits(4) AArch64.AllocationTagFromAddress(bits(64) tagged_address)">AArch64.AllocationTagFromAddress</a>(address);
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if writeback then
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if postindex then
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address = address + offset;
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if n == 31 then
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<a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = address;
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else
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<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[n, 64] = address;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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