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https://github.com/pound-emu/ballistic.git
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230 lines
14 KiB
XML
230 lines
14 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="stnt1h_z_p_ar" title="STNT1H (vector plus scalar)" type="instruction">
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<docvars>
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<docvar key="instr-class" value="sve2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STNT1H" />
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</docvars>
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<heading>STNT1H (vector plus scalar)</heading>
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<desc>
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<brief>Scatter store non-temporal halfwords</brief>
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<description>
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<para>Scatter store non-temporal of halfwords from the active elements of a vector register to the memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset. Inactive elements are not written to memory.</para>
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<para>A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.</para>
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<para>This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.</para>
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</description>
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<status>Green</status>
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<predicated>True</predicated>
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<sm_policy>SM_0_only</sm_policy>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from 2 classes:</txt>
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<a href="#iclass_off_s_x32_unscaled">32-bit unscaled offset</a>
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<txt> and </txt>
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<a href="#iclass_off_d_64_unscaled">64-bit unscaled offset</a>
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</classesintro>
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<iclass name="32-bit unscaled offset" oneof="2" id="iclass_off_s_x32_unscaled" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STNT1H" />
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<docvar key="sve-offset-type" value="off_s_x32_unscaled" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="STNT1H-Z.P.AR-S.x32.unscaled" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" name="msz<1>" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="23" name="msz<0>" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="20" width="5" name="Rm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="12" width="3" name="Pg" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="stnt1h_z_p_ar_s_x32_unscaled" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="instr-class" value="sve2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STNT1H" />
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<docvar key="sve-offset-type" value="off_s_x32_unscaled" />
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</docvars>
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<asmtemplate><text>STNT1H </text><text>{</text><text> </text><a link="sa_zt" hover="Scalable vector register to be transferred (field "Zt")"><Zt></a><text>.S </text><text>}</text><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>, [</text><a link="sa_zn" hover="Base scalable vector register (field "Zn")"><Zn></a><text>.S</text><text>{</text><text>, </text><a link="sa_xm" hover="Optional 64-bit general-purpose offset register, default XZR (field "Rm")"><Xm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="STNT1H-Z.P.AR-S.x32.unscaled" mylink="STNT1H-Z.P.AR-S.x32.unscaled" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2()">HaveSVE2</a>() then UNDEFINED;
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zt);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
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constant integer esize = 32;
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constant integer msize = 16;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="64-bit unscaled offset" oneof="2" id="iclass_off_d_64_unscaled" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STNT1H" />
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<docvar key="sve-offset-type" value="off_d_64_unscaled" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="STNT1H-Z.P.AR-D.64.unscaled" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" name="msz<1>" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="23" name="msz<0>" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" width="2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="20" width="5" name="Rm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="12" width="3" name="Pg" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="stnt1h_z_p_ar_d_64_unscaled" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="instr-class" value="sve2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STNT1H" />
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<docvar key="sve-offset-type" value="off_d_64_unscaled" />
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</docvars>
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<asmtemplate><text>STNT1H </text><text>{</text><text> </text><a link="sa_zt" hover="Scalable vector register to be transferred (field "Zt")"><Zt></a><text>.D </text><text>}</text><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>, [</text><a link="sa_zn" hover="Base scalable vector register (field "Zn")"><Zn></a><text>.D</text><text>{</text><text>, </text><a link="sa_xm" hover="Optional 64-bit general-purpose offset register, default XZR (field "Rm")"><Xm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="STNT1H-Z.P.AR-D.64.unscaled" mylink="STNT1H-Z.P.AR-D.64.unscaled" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2()">HaveSVE2</a>() then UNDEFINED;
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zt);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
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constant integer esize = 64;
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constant integer msize = 16;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="stnt1h_z_p_ar_d_64_unscaled, stnt1h_z_p_ar_s_x32_unscaled" symboldefcount="1">
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<symbol link="sa_zt"><Zt></symbol>
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<account encodedin="Zt">
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<intro>
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<para>Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="stnt1h_z_p_ar_d_64_unscaled, stnt1h_z_p_ar_s_x32_unscaled" symboldefcount="1">
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<symbol link="sa_pg"><Pg></symbol>
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<account encodedin="Pg">
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<intro>
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<para>Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="stnt1h_z_p_ar_d_64_unscaled, stnt1h_z_p_ar_s_x32_unscaled" symboldefcount="1">
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<symbol link="sa_zn"><Zn></symbol>
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<account encodedin="Zn">
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<intro>
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<para>Is the name of the base scalable vector register, encoded in the "Zn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="stnt1h_z_p_ar_d_64_unscaled, stnt1h_z_p_ar_s_x32_unscaled" symboldefcount="1">
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<symbol link="sa_xm"><Xm></symbol>
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<account encodedin="Rm">
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<intro>
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<para>Is the optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="STNT1H-Z.P.AR-S.x32.unscaled" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckNonStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
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constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
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constant integer PL = VL DIV 8;
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constant integer elements = VL DIV esize;
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bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
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bits(VL) base;
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bits(64) offset;
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bits(VL) src;
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constant integer mbytes = msize DIV 8;
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boolean contiguous = FALSE;
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boolean nontemporal = TRUE;
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boolean tagchecked = TRUE;
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<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescSVE.4" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescSVE(MemOp memop, boolean nontemporal, boolean contiguous, boolean tagchecked)">CreateAccDescSVE</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>, nontemporal, contiguous, tagchecked);
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if <a link="impl-aarch64.AnyActiveElement.2" file="shared_pseudocode.xml" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then
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base = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
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offset = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[m, 64];
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src = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[t, VL];
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for e = 0 to elements-1
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if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
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bits(64) addr = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[base, e, esize], 64) + offset;
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Mem[addr, mbytes, accdesc] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[src, e, esize]<msize-1:0>;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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