mirror of
https://github.com/pound-emu/ballistic.git
synced 2026-01-31 01:15:21 +01:00
189 lines
9.2 KiB
XML
189 lines
9.2 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
|
|
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
|
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
|
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
|
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
|
|
|
<instructionsection id="sub_z_zi" title="SUB (immediate)" type="instruction">
|
|
<docvars>
|
|
<docvar key="instr-class" value="sve" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="SUB" />
|
|
</docvars>
|
|
<heading>SUB (immediate)</heading>
|
|
<desc>
|
|
<brief>Subtract immediate (unpredicated)</brief>
|
|
<description>
|
|
<para>Subtract an unsigned immediate from each element of the source vector, and destructively place the results in the corresponding elements of the source vector. This instruction is unpredicated.</para>
|
|
<para>The immediate is an unsigned value in the range 0 to 255, and for element widths of 16 bits or higher it may also be a positive multiple of 256 in the range 256 to 65280.</para>
|
|
<para>The immediate is encoded in 8 bits with an optional left shift by 8. The preferred disassembly when the shift option is specified is "<syntax>#<uimm8>, LSL #8</syntax>". However an assembler and disassembler may also allow use of the shifted 16-bit value unless the immediate is 0 and the shift amount is 8, which must be unambiguously described as "<syntax>#0, LSL #8</syntax>".</para>
|
|
</description>
|
|
<status>Green</status>
|
|
<predicated>False</predicated>
|
|
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
|
<takes_movprfx>True</takes_movprfx>
|
|
</desc>
|
|
<alias_list howmany="0"></alias_list>
|
|
<classes>
|
|
<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
|
|
<docvars>
|
|
<docvar key="instr-class" value="sve" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="SUB" />
|
|
</docvars>
|
|
<iclassintro count="1"></iclassintro>
|
|
<regdiagram form="32" psname="SUB-Z.ZI-_">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="opc<2:1>" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" name="opc<0>" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" name="sh" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="8" name="imm8" usename="1">
|
|
<c colspan="8"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="sub_z_zi_" oneofinclass="1" oneof="1" label="">
|
|
<docvars>
|
|
<docvar key="instr-class" value="sve" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="SUB" />
|
|
</docvars>
|
|
<asmtemplate><text>SUB </text><a link="sa_zdn" hover="Source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_zdn" hover="Source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, #</text><a link="sa_imm" hover="Unsigned immediate [0-255] (field "imm8")"><imm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional left shift to apply to the immediate, default LSL #0 (field "sh") [LSL #0,LSL #8]"><shift></a><text>}</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="SUB-Z.ZI-_" mylink="SUB-Z.ZI-_" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
|
if size:sh == '001' then UNDEFINED;
|
|
constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
|
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
|
integer imm = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm8);
|
|
if sh == '1' then imm = imm << 8;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="sub_z_zi_" symboldefcount="1">
|
|
<symbol link="sa_zdn"><Zdn></symbol>
|
|
<account encodedin="Zdn">
|
|
<intro>
|
|
<para>Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="sub_z_zi_" symboldefcount="1">
|
|
<symbol link="sa_t"><T></symbol>
|
|
<definition encodedin="size">
|
|
<intro>Is the size specifier, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">size</entry>
|
|
<entry class="symbol"><T></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">B</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">H</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">D</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="sub_z_zi_" symboldefcount="1">
|
|
<symbol link="sa_imm"><imm></symbol>
|
|
<account encodedin="imm8">
|
|
<intro>
|
|
<para>Is an unsigned immediate in the range 0 to 255, encoded in the "imm8" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="sub_z_zi_" symboldefcount="1">
|
|
<symbol link="sa_shift"><shift></symbol>
|
|
<definition encodedin="sh">
|
|
<intro>Is the optional left shift to apply to the immediate, defaulting to LSL #0 and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">sh</entry>
|
|
<entry class="symbol"><shift></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">LSL #0</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">LSL #8</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="SUB-Z.ZI-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
|
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
|
constant integer elements = VL DIV esize;
|
|
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
|
bits(VL) result;
|
|
|
|
for e = 0 to elements-1
|
|
bits(esize) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
|
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - imm;
|
|
|
|
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|