mirror of
https://github.com/pound-emu/ballistic.git
synced 2026-01-31 01:15:21 +01:00
217 lines
11 KiB
XML
217 lines
11 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
|
|
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
|
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
|
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
|
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
|
|
|
<instructionsection id="SUDOT_advsimd_elt" title="SUDOT (by element) -- A64" type="instruction">
|
|
<docvars>
|
|
<docvar key="advsimd-reguse" value="2reg-element" />
|
|
<docvar key="instr-class" value="advsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="SUDOT" />
|
|
</docvars>
|
|
<heading>SUDOT (by element)</heading>
|
|
<desc>
|
|
<brief>
|
|
<para>Dot product with signed and unsigned integers (vector, by element)</para>
|
|
</brief>
|
|
<authored>
|
|
<para>Dot product index form with signed and unsigned integers. This instruction performs the dot product of the four signed 8-bit integer values in each 32-bit element of the first source register with the four unsigned 8-bit integer values in an indexed 32-bit element of the second source register, accumulating the result into the corresponding 32-bit element of the destination vector.</para>
|
|
<para>From Armv8.2 to Armv8.5, this is an <arm-defined-word>optional</arm-defined-word> instruction. From Armv8.6 it is mandatory for implementations that include Advanced SIMD to support it. <xref linkend="AArch64.id_aa64isar1_el1">ID_AA64ISAR1_EL1</xref>.I8MM indicates whether this instruction is supported.</para>
|
|
</authored>
|
|
</desc>
|
|
<alias_list howmany="0"></alias_list>
|
|
<classes>
|
|
<iclass name="Vector" oneof="1" id="iclass_2reg_element" no_encodings="1" isa="A64">
|
|
<docvars>
|
|
<docvar key="advsimd-reguse" value="2reg-element" />
|
|
<docvar key="instr-class" value="advsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="SUDOT" />
|
|
</docvars>
|
|
<iclassintro count="1"></iclassintro>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.6" feature="FEAT_I8MM" />
|
|
</arch_variants>
|
|
<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/binary/element/mat-mul/int/dotp" tworows="1">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="U" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="US" usename="1" settings="1" psbits="x">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="21" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="20" name="M" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Rm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="opcode" settings="4">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" name="H" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="SUDOT_asimdelem_D" oneofinclass="1" oneof="1" label="">
|
|
<docvars>
|
|
<docvar key="advsimd-reguse" value="2reg-element" />
|
|
<docvar key="instr-class" value="advsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="SUDOT" />
|
|
</docvars>
|
|
<asmtemplate><text>SUDOT </text><a link="sa_vd" hover="SIMD&FP third source and destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_ta" hover="Arrangement specifier (field "Q") [2S,4S]"><Ta></a><text>, </text><a link="sa_vn" hover="First SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_tb" hover="Arrangement specifier (field "Q") [8B,16B]"><Tb></a><text>, </text><a link="sa_vm" hover="Second SIMD&FP source register (field "M:Rm")"><Vm></a><text>.4B[</text><a link="sa_index" hover="Immediate index of a 32-bit group of four 8-bit values [0-3] (field "H:L")"><index></a><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/vector/arithmetic/binary/element/mat-mul/int/dotp" mylink="aarch64.instrs.vector.arithmetic.binary.element.mat-mul.int.dotp" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveInt8MatMulExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveInt8MatMulExt()">HaveInt8MatMulExt</a>() then UNDEFINED;
|
|
boolean op1_unsigned = (US == '1');
|
|
boolean op2_unsigned = (US == '0');
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
|
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Rm);
|
|
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
|
integer i = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(H:L);
|
|
integer datasize = if Q == '1' then 128 else 64;
|
|
integer elements = datasize DIV 32;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="SUDOT_asimdelem_D" symboldefcount="1">
|
|
<symbol link="sa_vd"><Vd></symbol>
|
|
<account encodedin="Rd">
|
|
<intro>
|
|
<para>Is the name of the SIMD&FP third source and destination register, encoded in the "Rd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="SUDOT_asimdelem_D" symboldefcount="1">
|
|
<symbol link="sa_ta"><Ta></symbol>
|
|
<definition encodedin="Q">
|
|
<intro>Is an arrangement specifier, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">Q</entry>
|
|
<entry class="symbol"><Ta></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">2S</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">4S</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="SUDOT_asimdelem_D" symboldefcount="1">
|
|
<symbol link="sa_vn"><Vn></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the name of the first SIMD&FP source register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="SUDOT_asimdelem_D" symboldefcount="1">
|
|
<symbol link="sa_tb"><Tb></symbol>
|
|
<definition encodedin="Q">
|
|
<intro>Is an arrangement specifier, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">Q</entry>
|
|
<entry class="symbol"><Tb></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">8B</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">16B</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="SUDOT_asimdelem_D" symboldefcount="1">
|
|
<symbol link="sa_vm"><Vm></symbol>
|
|
<account encodedin="M:Rm">
|
|
<intro>
|
|
<para>Is the name of the second SIMD&FP source register, encoded in the "M:Rm" fields.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="SUDOT_asimdelem_D" symboldefcount="1">
|
|
<symbol link="sa_index"><index></symbol>
|
|
<account encodedin="H:L">
|
|
<intro>
|
|
<para>Is the immediate index of a 32-bit group of four 8-bit values in the range 0 to 3, encoded in the "H:L" fields.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/vector/arithmetic/binary/element/mat-mul/int/dotp" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
|
|
bits(datasize) operand1 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
|
|
bits(128) operand2 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, 128];
|
|
bits(datasize) operand3 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[d, datasize];
|
|
bits(datasize) result;
|
|
|
|
for e = 0 to elements-1
|
|
bits(32) res = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 32];
|
|
for b = 0 to 3
|
|
integer element1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 4 * e + b, 8], op1_unsigned);
|
|
integer element2 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 4 * i + b, 8], op2_unsigned);
|
|
res = res + element1 * element2;
|
|
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = res;
|
|
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, datasize] = result;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|