archived-ballistic/spec/arm64_xml/sxtl_sshll_advsimd.xml

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<instructionsection id="SXTL_SSHLL_advsimd" title="SXTL, SXTL2 -- A64" type="alias">
  <docvars>
    <docvar key="advsimd-type" value="simd" />
    <docvar key="alias_mnemonic" value="SXTL" />
    <docvar key="instr-class" value="advsimd" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="SSHLL" />
  </docvars>
  <heading>SXTL, SXTL2</heading>
  <desc>
    <brief>
      <para>Signed extend Long</para>
    </brief>
    <authored>
      <para>Signed extend Long. This instruction duplicates each vector element in the lower or upper half of the source SIMD&amp;FP register into a vector, and writes the vector to the destination SIMD&amp;FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.</para>
      <para>The <instruction>SXTL</instruction> instruction extracts the source vector from the lower half of the source register. The <instruction>SXTL2</instruction> instruction extracts the source vector from the upper half of the source register.</para>
      <para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If PSTATE.DIT is 1:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <aliasto refiform="sshll_advsimd.xml" iformid="SSHLL_advsimd">SSHLL, SSHLL2</aliasto>
  <classes>
    <iclass name="Vector" oneof="1" id="iclass_simd" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="advsimd-type" value="simd" />
        <docvar key="instr-class" value="advsimd" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="SSHLL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/vector/shift/left-long" tworows="1">
        <box hibit="31" settings="1">
          <c>0</c>
        </box>
        <box hibit="30" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="29" name="U" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="28" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="4" name="immh" usename="1" settings="4" constraint="!= 0000">
          <c colspan="4">!= 0000</c>
        </box>
        <box hibit="18" width="3" name="immb" usename="1" settings="3" psbits="xxx">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="5" name="opcode" settings="5">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="SXTL_SSHLL_asimdshf_L" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="advsimd-type" value="simd" />
          <docvar key="alias_mnemonic" value="SXTL" />
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="SSHLL" />
        </docvars>
        <asmtemplate><text>SXTL</text><a link="sa_2" hover="Second and upper half specifier (field &quot;Q&quot;)">{2}</a><text>  </text><a link="sa_vd" hover="SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Vd&gt;</a><text>.</text><a link="sa_ta" hover="Arrangement specifier (field &quot;immh&quot;) [2D,4S,8H,SEE(asimdimm)]">&lt;Ta&gt;</a><text>, </text><a link="sa_vn" hover="SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Vn&gt;</a><text>.</text><a link="sa_tb" hover="Arrangement specifier (field &quot;immh:Q&quot;) [2S,4H,4S,8B,8H,16B,SEE(asimdimm)]">&lt;Tb&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="sshll_advsimd.xml#SSHLL_asimdshf_L">SSHLL</a><a link="sa_2" hover="Second and upper half specifier (field &quot;Q&quot;)">{2}</a><text>  </text><a link="sa_vd" hover="SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Vd&gt;</a><text>.</text><a link="sa_ta" hover="Arrangement specifier (field &quot;immh&quot;) [2D,4S,8H,SEE(asimdimm)]">&lt;Ta&gt;</a><text>, </text><a link="sa_vn" hover="SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Vn&gt;</a><text>.</text><a link="sa_tb" hover="Arrangement specifier (field &quot;immh:Q&quot;) [2S,4H,4S,8B,8H,16B,SEE(asimdimm)]">&lt;Tb&gt;</a><text>, #0</text></asmtemplate>
          <aliascond><a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(immh) == 1</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SXTL_SSHLL_asimdshf_L" symboldefcount="1">
      <symbol link="sa_2">2</symbol>
      <definition encodedin="Q">
        <intro>Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">Q</entry>
                <entry class="symbol">2</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">[absent]</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">[present]</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SXTL_SSHLL_asimdshf_L" symboldefcount="1">
      <symbol link="sa_vd">&lt;Vd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTL_SSHLL_asimdshf_L" symboldefcount="1">
      <symbol link="sa_ta">&lt;Ta&gt;</symbol>
      <definition encodedin="immh">
        <intro>Is an arrangement specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">immh</entry>
                <entry class="symbol">&lt;Ta&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0000</entry>
                <entry class="symbol" iclasslink="asimdimm" iclasslinkfile="encodingindex.xml">SEE Advanced SIMD modified immediate</entry>
              </row>
              <row>
                <entry class="bitfield">0001</entry>
                <entry class="symbol">8H</entry>
              </row>
              <row>
                <entry class="bitfield">001x</entry>
                <entry class="symbol">4S</entry>
              </row>
              <row>
                <entry class="bitfield">01xx</entry>
                <entry class="symbol">2D</entry>
              </row>
              <row>
                <entry class="bitfield">1xxx</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SXTL_SSHLL_asimdshf_L" symboldefcount="1">
      <symbol link="sa_vn">&lt;Vn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the name of the SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTL_SSHLL_asimdshf_L" symboldefcount="1">
      <symbol link="sa_tb">&lt;Tb&gt;</symbol>
      <definition encodedin="immh:Q">
        <intro>Is an arrangement specifier, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">immh</entry>
                <entry class="bitfield">Q</entry>
                <entry class="symbol">&lt;Tb&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0000</entry>
                <entry class="bitfield">x</entry>
                <entry class="symbol" iclasslink="asimdimm" iclasslinkfile="encodingindex.xml">SEE Advanced SIMD modified immediate</entry>
              </row>
              <row>
                <entry class="bitfield">0001</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">8B</entry>
              </row>
              <row>
                <entry class="bitfield">0001</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">16B</entry>
              </row>
              <row>
                <entry class="bitfield">001x</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">4H</entry>
              </row>
              <row>
                <entry class="bitfield">001x</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">8H</entry>
              </row>
              <row>
                <entry class="bitfield">01xx</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">2S</entry>
              </row>
              <row>
                <entry class="bitfield">01xx</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">4S</entry>
              </row>
              <row>
                <entry class="bitfield">1xxx</entry>
                <entry class="bitfield">x</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
</instructionsection>