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Ronald Caesar 26a677f8b4 decoder: Add ARM specification docs
Signed-off-by: Ronald Caesar <github43132@proton.me>
2025-12-12 18:11:36 -04:00

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<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<instructionsection id="SYSL" title="SYSL -- A64" type="instruction">
<docvars>
<docvar key="instr-class" value="system" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="SYSL" />
</docvars>
<heading>SYSL</heading>
<desc>
<brief>
<para>System instruction with result</para>
</brief>
<authored>
<para>System instruction with result. For more information, see <xref linkend="BABEJJJE">Op0 equals 0b01, cache maintenance, TLB maintenance, and address translation instructions</xref> for the encodings of System instructions.</para>
</authored>
</desc>
<alias_list howmany="2">
<alias_list_intro>This instruction is used by the aliases </alias_list_intro>
<aliasref aliaspageid="GCSPOPM_SYSL" aliasfile="gcspopm_sysl.xml" hover="GCSPOPM" punct=" and ">
<text>GCSPOPM</text>
<aliaspref>op1 == '011' &amp;&amp; CRn == '0111' &amp;&amp; CRm == '0111' &amp;&amp; op2 == '001'</aliaspref>
</aliasref>
<aliasref aliaspageid="GCSSS2_SYSL" aliasfile="gcsss2_sysl.xml" hover="GCSSS2" punct=".">
<text>GCSSS2</text>
<aliaspref>op1 == '011' &amp;&amp; CRn == '0111' &amp;&amp; CRm == '0111' &amp;&amp; op2 == '011'</aliaspref>
</aliasref>
<alias_list_outro>
<text> See </text>
<aliastablelink />
<text> below for details of when each alias is preferred.</text>
</alias_list_outro>
</alias_list>
<classes>
<iclass name="System" oneof="1" id="iclass_system" no_encodings="1" isa="A64">
<docvars>
<docvar key="instr-class" value="system" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="SYSL" />
</docvars>
<iclassintro count="1"></iclassintro>
<regdiagram form="32" psname="aarch64/instrs/system/sysops" tworows="1">
<box hibit="31" width="10" settings="10">
<c>1</c>
<c>1</c>
<c>0</c>
<c>1</c>
<c>0</c>
<c>1</c>
<c>0</c>
<c>1</c>
<c>0</c>
<c>0</c>
</box>
<box hibit="21" name="L" usename="1" settings="1" psbits="x">
<c>1</c>
</box>
<box hibit="20" width="2" name="op0" settings="2">
<c>0</c>
<c>1</c>
</box>
<box hibit="18" width="3" name="op1" usename="1">
<c colspan="3"></c>
</box>
<box hibit="15" width="4" name="CRn" usename="1">
<c colspan="4"></c>
</box>
<box hibit="11" width="4" name="CRm" usename="1">
<c colspan="4"></c>
</box>
<box hibit="7" width="3" name="op2" usename="1">
<c colspan="3"></c>
</box>
<box hibit="4" width="5" name="Rt" usename="1">
<c colspan="5"></c>
</box>
</regdiagram>
<encoding name="SYSL_RC_systeminstrs" oneofinclass="1" oneof="1" label="">
<docvars>
<docvar key="instr-class" value="system" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="SYSL" />
</docvars>
<asmtemplate><text>SYSL </text><a link="sa_xt" hover="64-bit general-purpose destination register (field &quot;Rt&quot;)">&lt;Xt&gt;</a><text>, #</text><a link="sa_op1" hover="3-bit unsigned immediate [0-7] (field &quot;op1&quot;)">&lt;op1&gt;</a><text>, </text><a link="sa_cn" hover="Name 'Cn', with 'n' [0-15] (field &quot;CRn&quot;)">&lt;Cn&gt;</a><text>, </text><a link="sa_cm" hover="Name 'Cm', with 'm' [0-15] (field &quot;CRm&quot;)">&lt;Cm&gt;</a><text>, #</text><a link="sa_op2" hover="3-bit unsigned immediate [0-7] (field &quot;op2&quot;)">&lt;op2&gt;</a></asmtemplate>
</encoding>
<ps_section howmany="1">
<ps name="aarch64/instrs/system/sysops" mylink="aarch64.instrs.system.sysops" enclabels="" sections="1" secttype="noheading">
<pstext mayhavelinks="1" section="Decode" rep_section="decode"><a link="AArch64.CheckSystemAccess.7" file="shared_pseudocode.xml" hover="function: AArch64.CheckSystemAccess(bits(2) op0, bits(3) op1, bits(4) crn, bits(4) crm, bits(3) op2, bits(5) rt, bit read)">AArch64.CheckSystemAccess</a>('01', op1, CRn, CRm, op2, Rt, L);
integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
integer sys_op0 = 1;
integer sys_op1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op1);
integer sys_op2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op2);
integer sys_crn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(CRn);
integer sys_crm = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(CRm);
boolean has_result = (L == '1');</pstext>
</ps>
</ps_section>
</iclass>
</classes>
<explanations scope="all">
<explanation enclist="SYSL_RC_systeminstrs" symboldefcount="1">
<symbol link="sa_xt">&lt;Xt&gt;</symbol>
<account encodedin="Rt">
<intro>
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rt" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="SYSL_RC_systeminstrs" symboldefcount="1">
<symbol link="sa_op1">&lt;op1&gt;</symbol>
<account encodedin="op1">
<intro>
<para>Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op1" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="SYSL_RC_systeminstrs" symboldefcount="1">
<symbol link="sa_cn">&lt;Cn&gt;</symbol>
<account encodedin="CRn">
<intro>
<para>Is a name 'Cn', with 'n' in the range 0 to 15, encoded in the "CRn" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="SYSL_RC_systeminstrs" symboldefcount="1">
<symbol link="sa_cm">&lt;Cm&gt;</symbol>
<account encodedin="CRm">
<intro>
<para>Is a name 'Cm', with 'm' in the range 0 to 15, encoded in the "CRm" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="SYSL_RC_systeminstrs" symboldefcount="1">
<symbol link="sa_op2">&lt;op2&gt;</symbol>
<account encodedin="op2">
<intro>
<para>Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.</para>
</intro>
</account>
</explanation>
</explanations>
<aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
<ps_section howmany="1">
<ps name="aarch64/instrs/system/sysops" mylink="execute" enclabels="" sections="1" secttype="Operation">
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if has_result then
// No architecturally defined instructions here.
<a link="AArch64.SysInstrWithResult.6" file="shared_pseudocode.xml" hover="function: AArch64.SysInstrWithResult(integer op0, integer op1, integer crn, integer crm, integer op2, integer t)">AArch64.SysInstrWithResult</a>(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, t);
else
<a link="AArch64.SysInstr.6" file="shared_pseudocode.xml" hover="function: AArch64.SysInstr(integer op0, integer op1, integer crn, integer crm, integer op2, integer t)">AArch64.SysInstr</a>(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, t);</pstext>
</ps>
</ps_section>
</instructionsection>