archived-ballistic/spec/arm64_xml/tbnz.xml

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<instructionsection id="TBNZ" title="TBNZ -- A64" type="instruction">
  <docvars>
    <docvar key="branch-offset" value="br14" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="TBNZ" />
  </docvars>
  <heading>TBNZ</heading>
  <desc>
    <brief>
      <para>Test bit and Branch if Nonzero</para>
    </brief>
    <authored>
      <para>Test bit and Branch if Nonzero compares the value of a bit in a general-purpose register with zero, and conditionally branches to a label at a PC-relative offset if the comparison is not equal. It provides a hint that this is not a subroutine call or return. This instruction does not affect condition flags.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="14-bit signed PC-relative branch offset" oneof="1" id="iclass_br14" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="branch-offset" value="br14" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="TBNZ" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch64/instrs/branch/conditional/test" tworows="1">
        <box hibit="31" name="b5" usename="1">
          <c></c>
        </box>
        <box hibit="30" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="24" name="op" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="23" width="5" name="b40" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="18" width="14" name="imm14" usename="1">
          <c colspan="14"></c>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="TBNZ_only_testbranch" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="branch-offset" value="br14" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="TBNZ" />
        </docvars>
        <asmtemplate><text>TBNZ  </text><a link="sa_r" hover="Width specifier (field &quot;b5&quot;) [W,X]">&lt;R&gt;</a><a link="sa_t" hover="General-purpose register number [0-30] to be tested or ZR (31) (field &quot;Rt&quot;)">&lt;t&gt;</a><text>, #</text><a link="sa_imm" hover="Bit number to be tested [0-63] (field &quot;b5:b40&quot;)">&lt;imm&gt;</a><text>, </text><a link="sa_label" hover="Label to be conditionally branched to (field imm14)">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/branch/conditional/test" mylink="aarch64.instrs.branch.conditional.test" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);

integer datasize = if b5 == '1' then 64 else 32;
integer bit_pos = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(b5:b40);
bit bit_val = op;
bits(64) offset = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm14:'00', 64);</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="TBNZ_only_testbranch" symboldefcount="1">
      <symbol link="sa_r">&lt;R&gt;</symbol>
      <definition encodedin="b5">
        <intro>Is a width specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">b5</entry>
                <entry class="symbol">&lt;R&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">W</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">X</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
        <after>In assembler source code an 'X' specifier is always permitted, but a 'W' specifier is only permitted when the bit number is less than 32.</after>
      </definition>
    </explanation>
    <explanation enclist="TBNZ_only_testbranch" symboldefcount="1">
      <symbol link="sa_t">&lt;t&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the number [0-30] of the general-purpose register to be tested or the name ZR (31), encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TBNZ_only_testbranch" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="b40:b5">
        <intro>
          <para>Is the bit number to be tested, in the range 0 to 63, encoded in "b5:b40".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TBNZ_only_testbranch" symboldefcount="1">
      <symbol link="sa_label">&lt;label&gt;</symbol>
      <account encodedin="imm14">
        <intro>
          <para>Is the program label to be conditionally branched to. Its offset from the address of this instruction, in the range +/-32KB, is encoded as "imm14" times 4.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/branch/conditional/test" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(datasize) operand = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[t, datasize];
boolean branch_conditional = TRUE;
if operand&lt;bit_pos&gt; == bit_val then
    <a link="impl-shared.BranchTo.3" file="shared_pseudocode.xml" hover="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(<a link="impl-aarch64.PC.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) PC[]">PC</a>[] + offset, <a link="BranchType_DIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a>, branch_conditional);
else
    <a link="impl-shared.BranchNotTaken.2" file="shared_pseudocode.xml" hover="function: BranchNotTaken(BranchType branchtype, boolean branch_conditional)">BranchNotTaken</a>(<a link="BranchType_DIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a>, branch_conditional);</pstext>
    </ps>
  </ps_section>
</instructionsection>