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107 lines
4.0 KiB
XML
107 lines
4.0 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="TRCIT_SYS" title="TRCIT -- A64" type="alias">
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<docvars>
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<docvar key="alias_mnemonic" value="TRCIT" />
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<docvar key="instr-class" value="system" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SYS" />
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</docvars>
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<heading>TRCIT</heading>
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<desc>
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<brief>
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<para>Trace Instrumentation</para>
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</brief>
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<authored>
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<para>Trace Instrumentation generates an instrumentation trace packet that contains the value of the provided register.</para>
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</authored>
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</desc>
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<aliasto refiform="sys.xml" iformid="SYS">SYS</aliasto>
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<classes>
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<iclass name="System" oneof="1" id="iclass_system" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="system" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SYS" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="FEAT_ITE" feature="FEAT_ITE" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/system/sysops" tworows="1">
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<box hibit="31" width="10" settings="10">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="21" name="L" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="20" width="2" name="op0" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="18" width="3" name="op1" usename="1" settings="3" psbits="xxx">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="15" width="4" name="CRn" usename="1" settings="4" psbits="xxxx">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="11" width="4" name="CRm" usename="1" settings="4" psbits="xxxx">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="7" width="3" name="op2" usename="1" settings="3" psbits="xxx">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="4" width="5" name="Rt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="TRCIT_SYS_CR_systeminstrs" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="alias_mnemonic" value="TRCIT" />
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<docvar key="instr-class" value="system" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SYS" />
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</docvars>
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<asmtemplate><text>TRCIT </text><a link="sa_xt_1" hover="64-bit general-purpose source register (field "Rt")"><Xt></a></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="sys.xml#SYS_CR_systeminstrs">SYS</a><text> #3, C7, C2, #7, </text><a link="sa_xt_1" hover="64-bit general-purpose source register (field "Rt")"><Xt></a></asmtemplate>
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<aliascond>Unconditionally</aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="TRCIT_SYS_CR_systeminstrs" symboldefcount="1">
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<symbol link="sa_xt_1"><Xt></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the 64-bit name of the general-purpose source register, encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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</instructionsection>
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