mirror of
https://github.com/pound-emu/ballistic.git
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387 lines
20 KiB
XML
387 lines
20 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="trn1_z_zz" title="TRN1, TRN2 (vectors)" type="instruction">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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</docvars>
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<heading>TRN1, TRN2 (vectors)</heading>
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<desc>
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<brief>Interleave even or odd elements from two vectors</brief>
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<description>
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<para>Interleave alternating even or odd-numbered elements from the first and second source vectors and place in elements of the destination vector. This instruction is unpredicated.</para>
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<para>The 128-bit element variant requires that the current vector length is at least 256 bits, and if the current vector length is not an integer multiple of 256 bits then the trailing bits are set to zero. ID_AA64ZFR0_EL1.F64MM indicates whether the 128-bit element variant is implemented. The 128-bit element variant is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.</para>
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</description>
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<status>Green</status>
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<predicated>False</predicated>
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<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
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<sm_policy>SM_0_only</sm_policy>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="4">
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<txt>It has encodings from 4 classes:</txt>
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<a href="#iclass_sve_even">Even</a>
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<txt>, </txt>
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<a href="#iclass_sve_even_quad">Even (quadwords)</a>
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<txt>, </txt>
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<a href="#iclass_sve_odd">Odd</a>
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<txt> and </txt>
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<a href="#iclass_sve_odd_quad">Odd (quadwords)</a>
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</classesintro>
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<iclass name="Even" oneof="4" id="iclass_sve_even" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="TRN1" />
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<docvar key="sve-odd-even" value="sve-even" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="TRN1-Z.ZZ-_" tworows="1">
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<box hibit="31" width="8" settings="8">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="23" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Zm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="3" settings="3">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="12" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="10" name="H" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="trn1_z_zz_" oneofinclass="1" oneof="4" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="TRN1" />
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<docvar key="sve-odd-even" value="sve-even" />
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</docvars>
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<asmtemplate><text>TRN1 </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="TRN1-Z.ZZ-_" mylink="TRN1-Z.ZZ-_" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
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constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);
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integer part = 0;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Even (quadwords)" oneof="4" id="iclass_sve_even_quad" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="TRN1" />
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<docvar key="sve-odd-even" value="sve-even-quad" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.6" feature="FEAT_F64MM" />
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</arch_variants>
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<regdiagram form="32" psname="TRN1-Z.ZZ-Q" tworows="1">
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<box hibit="31" width="11" settings="11">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Zm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="12" name="opc<1>" settings="1">
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<c>1</c>
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</box>
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<box hibit="11" name="opc<0>" settings="1">
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<c>1</c>
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</box>
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<box hibit="10" name="H" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="trn1_z_zz_q" oneofinclass="1" oneof="4" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="TRN1" />
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<docvar key="sve-odd-even" value="sve-even-quad" />
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</docvars>
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<asmtemplate><text>TRN1 </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.Q, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.Q, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.Q</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="TRN1-Z.ZZ-Q" mylink="TRN1-Z.ZZ-Q" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() || !<a link="impl-aarch64.HaveSVEFP64MatMulExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVEFP64MatMulExt()">HaveSVEFP64MatMulExt</a>() then UNDEFINED;
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constant integer esize = 128;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);
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integer part = 0;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Odd" oneof="4" id="iclass_sve_odd" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="TRN2" />
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<docvar key="sve-odd-even" value="sve-odd" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="TRN2-Z.ZZ-_" tworows="1">
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<box hibit="31" width="8" settings="8">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="23" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Zm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="3" settings="3">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="12" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="10" name="H" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="trn2_z_zz_" oneofinclass="1" oneof="4" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="TRN2" />
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<docvar key="sve-odd-even" value="sve-odd" />
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</docvars>
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<asmtemplate><text>TRN2 </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="TRN2-Z.ZZ-_" mylink="TRN2-Z.ZZ-_" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
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constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);
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integer part = 1;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Odd (quadwords)" oneof="4" id="iclass_sve_odd_quad" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="TRN2" />
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<docvar key="sve-odd-even" value="sve-odd-quad" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.6" feature="FEAT_F64MM" />
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</arch_variants>
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<regdiagram form="32" psname="TRN2-Z.ZZ-Q" tworows="1">
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<box hibit="31" width="11" settings="11">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Zm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="12" name="opc<1>" settings="1">
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<c>1</c>
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</box>
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<box hibit="11" name="opc<0>" settings="1">
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<c>1</c>
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</box>
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<box hibit="10" name="H" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="trn2_z_zz_q" oneofinclass="1" oneof="4" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="TRN2" />
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<docvar key="sve-odd-even" value="sve-odd-quad" />
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</docvars>
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<asmtemplate><text>TRN2 </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.Q, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.Q, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.Q</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="TRN2-Z.ZZ-Q" mylink="TRN2-Z.ZZ-Q" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() || !<a link="impl-aarch64.HaveSVEFP64MatMulExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVEFP64MatMulExt()">HaveSVEFP64MatMulExt</a>() then UNDEFINED;
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constant integer esize = 128;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);
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integer part = 1;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="trn1_z_zz_q, trn1_z_zz_, trn2_z_zz_q, trn2_z_zz_" symboldefcount="1">
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<symbol link="sa_zd"><Zd></symbol>
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<account encodedin="Zd">
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<intro>
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<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="trn1_z_zz_, trn2_z_zz_" symboldefcount="1">
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<symbol link="sa_t"><T></symbol>
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<definition encodedin="size">
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<intro>Is the size specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">size</entry>
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<entry class="symbol"><T></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="symbol">B</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="symbol">H</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="symbol">S</entry>
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</row>
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<row>
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<entry class="bitfield">11</entry>
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<entry class="symbol">D</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="trn1_z_zz_q, trn1_z_zz_, trn2_z_zz_q, trn2_z_zz_" symboldefcount="1">
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<symbol link="sa_zn"><Zn></symbol>
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<account encodedin="Zn">
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<intro>
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<para>Is the name of the first source scalable vector register, encoded in the "Zn" field.</para>
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</intro>
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</account>
|
|
</explanation>
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|
<explanation enclist="trn1_z_zz_q, trn1_z_zz_, trn2_z_zz_q, trn2_z_zz_" symboldefcount="1">
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|
<symbol link="sa_zm"><Zm></symbol>
|
|
<account encodedin="Zm">
|
|
<intro>
|
|
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="TRN1-Z.ZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if esize < 128 then <a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>(); else <a link="impl-aarch64.CheckNonStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
|
|
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
|
if VL < esize * 2 then UNDEFINED;
|
|
constant integer pairs = VL DIV (esize * 2);
|
|
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
|
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
|
bits(VL) result = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
|
|
|
for p = 0 to pairs-1
|
|
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+0, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*p+part, esize];
|
|
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p+1, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*p+part, esize];
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|
|
|
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|