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https://github.com/pound-emu/ballistic.git
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153 lines
6.8 KiB
XML
153 lines
6.8 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="TST_ANDS_log_imm" title="TST (immediate) -- A64" type="alias">
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<docvars>
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<docvar key="alias_mnemonic" value="TST" />
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<docvar key="cond-setting" value="S" />
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<docvar key="immediate-type" value="imm12-bitfield" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ANDS" />
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</docvars>
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<heading>TST (immediate)</heading>
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<desc>
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<brief>Test bits (immediate)</brief>
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<alg>Rn AND imm</alg>
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<longer>, setting the condition flags and discarding the result</longer>
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</desc>
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<aliasto refiform="ands_log_imm.xml" iformid="ANDS_log_imm">ANDS (immediate)</aliasto>
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<classes>
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<iclass name="Setting the condition flags" oneof="1" id="iclass_s" no_encodings="2" isa="A64">
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<docvars>
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<docvar key="cond-setting" value="S" />
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<docvar key="immediate-type" value="imm12-bitfield" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ANDS" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/integer/logical/immediate" tworows="1">
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<box hibit="31" name="sf" usename="1">
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<c></c>
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</box>
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<box hibit="30" width="2" name="opc" usename="1" settings="2" psbits="xx">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="28" width="6" settings="6">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="22" name="N" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="6" name="immr" usename="1">
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<c colspan="6"></c>
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</box>
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<box hibit="15" width="6" name="imms" usename="1">
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<c colspan="6"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1" settings="5" psbits="xxxxx">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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</regdiagram>
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<encoding name="TST_ANDS_32S_log_imm" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0 && N == 0">
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<docvars>
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<docvar key="alias_mnemonic" value="TST" />
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<docvar key="cond-setting" value="S" />
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<docvar key="datatype" value="32" />
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<docvar key="immediate-type" value="imm12-bitfield" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ANDS" />
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</docvars>
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<box hibit="31" width="1" name="sf">
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<c>0</c>
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</box>
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<box hibit="22" width="1" name="N">
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<c>0</c>
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</box>
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<asmtemplate><text>TST </text><a link="sa_wn" hover="32-bit general-purpose source register (field "Rn")"><Wn></a><text>, #</text><a link="sa_imm" hover="Bitmask immediate (field "imms:immr")"><imm></a></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="ands_log_imm.xml#ANDS_32S_log_imm">ANDS</a><text> WZR, </text><a link="sa_wn" hover="32-bit general-purpose source register (field "Rn")"><Wn></a><text>, #</text><a link="sa_imm" hover="Bitmask immediate (field "imms:immr")"><imm></a></asmtemplate>
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<aliascond>Unconditionally</aliascond>
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</equivalent_to>
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</encoding>
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<encoding name="TST_ANDS_64S_log_imm" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
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<docvars>
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<docvar key="alias_mnemonic" value="TST" />
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<docvar key="cond-setting" value="S" />
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<docvar key="datatype" value="64" />
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<docvar key="immediate-type" value="imm12-bitfield" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ANDS" />
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</docvars>
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<box hibit="31" width="1" name="sf">
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<c>1</c>
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</box>
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<asmtemplate><text>TST </text><a link="sa_xn" hover="64-bit general-purpose source register (field "Rn")"><Xn></a><text>, #</text><a link="sa_imm_1" hover="Bitmask immediate (field "N:imms:immr")"><imm></a></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="ands_log_imm.xml#ANDS_64S_log_imm">ANDS</a><text> XZR, </text><a link="sa_xn" hover="64-bit general-purpose source register (field "Rn")"><Xn></a><text>, #</text><a link="sa_imm_1" hover="Bitmask immediate (field "N:imms:immr")"><imm></a></asmtemplate>
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<aliascond>Unconditionally</aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="TST_ANDS_32S_log_imm" symboldefcount="1">
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<symbol link="sa_wn"><Wn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="TST_ANDS_64S_log_imm" symboldefcount="1">
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<symbol link="sa_xn"><Xn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="TST_ANDS_32S_log_imm" symboldefcount="1">
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<symbol link="sa_imm"><imm></symbol>
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<account encodedin="immr:imms">
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<docvars>
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<docvar key="datatype" value="32" />
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</docvars>
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<intro>
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<para>For the 32-bit variant: is the bitmask immediate, encoded in "imms:immr".</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="TST_ANDS_64S_log_imm" symboldefcount="2">
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<symbol link="sa_imm_1"><imm></symbol>
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<account encodedin="N:immr:imms">
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<docvars>
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<docvar key="datatype" value="64" />
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</docvars>
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<intro>
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<para>For the 64-bit variant: is the bitmask immediate, encoded in "N:imms:immr".</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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</instructionsection>
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