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archived-ballistic/spec/arm64_xml/tst_ands_log_imm.xml
Ronald Caesar 26a677f8b4 decoder: Add ARM specification docs
Signed-off-by: Ronald Caesar <github43132@proton.me>
2025-12-12 18:11:36 -04:00

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XML

<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<instructionsection id="TST_ANDS_log_imm" title="TST (immediate) -- A64" type="alias">
<docvars>
<docvar key="alias_mnemonic" value="TST" />
<docvar key="cond-setting" value="S" />
<docvar key="immediate-type" value="imm12-bitfield" />
<docvar key="instr-class" value="general" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="ANDS" />
</docvars>
<heading>TST (immediate)</heading>
<desc>
<brief>Test bits (immediate)</brief>
<alg>Rn AND imm</alg>
<longer>, setting the condition flags and discarding the result</longer>
</desc>
<aliasto refiform="ands_log_imm.xml" iformid="ANDS_log_imm">ANDS (immediate)</aliasto>
<classes>
<iclass name="Setting the condition flags" oneof="1" id="iclass_s" no_encodings="2" isa="A64">
<docvars>
<docvar key="cond-setting" value="S" />
<docvar key="immediate-type" value="imm12-bitfield" />
<docvar key="instr-class" value="general" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="ANDS" />
</docvars>
<iclassintro count="2"></iclassintro>
<regdiagram form="32" psname="aarch64/instrs/integer/logical/immediate" tworows="1">
<box hibit="31" name="sf" usename="1">
<c></c>
</box>
<box hibit="30" width="2" name="opc" usename="1" settings="2" psbits="xx">
<c>1</c>
<c>1</c>
</box>
<box hibit="28" width="6" settings="6">
<c>1</c>
<c>0</c>
<c>0</c>
<c>1</c>
<c>0</c>
<c>0</c>
</box>
<box hibit="22" name="N" usename="1">
<c></c>
</box>
<box hibit="21" width="6" name="immr" usename="1">
<c colspan="6"></c>
</box>
<box hibit="15" width="6" name="imms" usename="1">
<c colspan="6"></c>
</box>
<box hibit="9" width="5" name="Rn" usename="1">
<c colspan="5"></c>
</box>
<box hibit="4" width="5" name="Rd" usename="1" settings="5" psbits="xxxxx">
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
</box>
</regdiagram>
<encoding name="TST_ANDS_32S_log_imm" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0 &amp;&amp; N == 0">
<docvars>
<docvar key="alias_mnemonic" value="TST" />
<docvar key="cond-setting" value="S" />
<docvar key="datatype" value="32" />
<docvar key="immediate-type" value="imm12-bitfield" />
<docvar key="instr-class" value="general" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="ANDS" />
</docvars>
<box hibit="31" width="1" name="sf">
<c>0</c>
</box>
<box hibit="22" width="1" name="N">
<c>0</c>
</box>
<asmtemplate><text>TST </text><a link="sa_wn" hover="32-bit general-purpose source register (field &quot;Rn&quot;)">&lt;Wn&gt;</a><text>, #</text><a link="sa_imm" hover="Bitmask immediate (field &quot;imms:immr&quot;)">&lt;imm&gt;</a></asmtemplate>
<equivalent_to>
<asmtemplate><a href="ands_log_imm.xml#ANDS_32S_log_imm">ANDS</a><text> WZR, </text><a link="sa_wn" hover="32-bit general-purpose source register (field &quot;Rn&quot;)">&lt;Wn&gt;</a><text>, #</text><a link="sa_imm" hover="Bitmask immediate (field &quot;imms:immr&quot;)">&lt;imm&gt;</a></asmtemplate>
<aliascond>Unconditionally</aliascond>
</equivalent_to>
</encoding>
<encoding name="TST_ANDS_64S_log_imm" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
<docvars>
<docvar key="alias_mnemonic" value="TST" />
<docvar key="cond-setting" value="S" />
<docvar key="datatype" value="64" />
<docvar key="immediate-type" value="imm12-bitfield" />
<docvar key="instr-class" value="general" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="ANDS" />
</docvars>
<box hibit="31" width="1" name="sf">
<c>1</c>
</box>
<asmtemplate><text>TST </text><a link="sa_xn" hover="64-bit general-purpose source register (field &quot;Rn&quot;)">&lt;Xn&gt;</a><text>, #</text><a link="sa_imm_1" hover="Bitmask immediate (field &quot;N:imms:immr&quot;)">&lt;imm&gt;</a></asmtemplate>
<equivalent_to>
<asmtemplate><a href="ands_log_imm.xml#ANDS_64S_log_imm">ANDS</a><text> XZR, </text><a link="sa_xn" hover="64-bit general-purpose source register (field &quot;Rn&quot;)">&lt;Xn&gt;</a><text>, #</text><a link="sa_imm_1" hover="Bitmask immediate (field &quot;N:imms:immr&quot;)">&lt;imm&gt;</a></asmtemplate>
<aliascond>Unconditionally</aliascond>
</equivalent_to>
</encoding>
</iclass>
</classes>
<explanations scope="all">
<explanation enclist="TST_ANDS_32S_log_imm" symboldefcount="1">
<symbol link="sa_wn">&lt;Wn&gt;</symbol>
<account encodedin="Rn">
<intro>
<para>Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="TST_ANDS_64S_log_imm" symboldefcount="1">
<symbol link="sa_xn">&lt;Xn&gt;</symbol>
<account encodedin="Rn">
<intro>
<para>Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="TST_ANDS_32S_log_imm" symboldefcount="1">
<symbol link="sa_imm">&lt;imm&gt;</symbol>
<account encodedin="immr:imms">
<docvars>
<docvar key="datatype" value="32" />
</docvars>
<intro>
<para>For the 32-bit variant: is the bitmask immediate, encoded in "imms:immr".</para>
</intro>
</account>
</explanation>
<explanation enclist="TST_ANDS_64S_log_imm" symboldefcount="2">
<symbol link="sa_imm_1">&lt;imm&gt;</symbol>
<account encodedin="N:immr:imms">
<docvars>
<docvar key="datatype" value="64" />
</docvars>
<intro>
<para>For the 64-bit variant: is the bitmask immediate, encoded in "N:imms:immr".</para>
</intro>
</account>
</explanation>
</explanations>
</instructionsection>