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https://github.com/pound-emu/ballistic.git
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395 lines
22 KiB
XML
395 lines
22 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="umlsll_za_zzw" title="UMLSLL (multiple vectors)" type="instruction">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="UMLSLL" />
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</docvars>
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<heading>UMLSLL (multiple vectors)</heading>
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<desc>
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<brief>Multi-vector unsigned integer multiply-subtract long long</brief>
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<description>
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<para>The instruction operates on two or four ZA quad-vector groups.</para>
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<para>This unsigned integer multiply-subtract long long instruction multiplies each unsigned 8-bit or 16-bit element in the two or four first source vectors with each unsigned 8-bit or 16-bit element in the one, two, or four second source vectors, widens each product to 32-bits or 64-bits and destructively subtracts these values from the corresponding 32-bit or 64-bit elements of the two or four ZA quad-vector groups. The lowest of the four consecutive vector numbers forming the quad-vector group within each half or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo half or quarter the number of ZA array vectors.</para>
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<para>The <arm-defined-word>vector group</arm-defined-word> symbol, <syntax>VGx2</syntax> or <syntax>VGx4</syntax>, indicates that the ZA operand consists of two or four ZA quad-vector groups respectively. The <arm-defined-word>vector group</arm-defined-word> symbol is preferred for disassembly, but optional in assembler source code.</para>
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<para>This instruction is unpredicated.</para>
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<para>ID_AA64SMFR0_EL1.I16I64 indicates whether the 16-bit integer variant is implemented.</para>
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</description>
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<status>Green</status>
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<predicated>False</predicated>
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<sm_policy>SM_1_only</sm_policy>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from 2 classes:</txt>
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<a href="#iclass_sme_vgx2_quad">Two ZA quad-vectors</a>
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<txt> and </txt>
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<a href="#iclass_sme_vgx4_quad">Four ZA quad-vectors</a>
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</classesintro>
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<iclass name="Two ZA quad-vectors" oneof="2" id="iclass_sme_vgx2_quad" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="UMLSLL" />
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<docvar key="sme-multireg" value="sme-vgx2-quad" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
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</arch_variants>
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<regdiagram form="32" psname="UMLSLL-ZA.ZZW-2x2" tworows="1">
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<box hibit="31" width="9" settings="9">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="22" name="sz" usename="1">
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<c></c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="4" name="Zm" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="16" width="2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="14" width="2" name="Rv" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="12" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="9" width="4" name="Zn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="5" settings="1">
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<c>0</c>
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</box>
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<box hibit="4" name="U" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" name="S" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="2" name="op" settings="1">
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<c>0</c>
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</box>
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<box hibit="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="0" name="o1" usename="1">
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<c></c>
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</box>
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</regdiagram>
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<encoding name="umlsll_za_zzw_2x2" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="UMLSLL" />
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<docvar key="sme-multireg" value="sme-vgx2-quad" />
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</docvars>
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<asmtemplate><text>UMLSLL ZA.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offsf" hover="Vector select offset, pointing to first of four consecutive vectors, encoded as "o1" field times 4 (field o1)"><offsf></a><text>:</text><a link="sa_offsl" hover="Vector select offset, pointing to last of four consecutive vectors, encoded as "o1" field times 4 plus 3 (field o1)"><offsl></a><a>{, VGx2}</a><text>], </text><text>{</text><text> </text><a link="sa_zn1" hover="First scalable vector register of a multi-vector sequence (field Zn)"><Zn1></a><text>.</text><a link="sa_tb" hover="Size specifier (field "sz") [B,H]"><Tb></a><text>-</text><a link="sa_zn2" hover="Second scalable vector register of a multi-vector sequence (field Zn)"><Zn2></a><text>.</text><a link="sa_tb" hover="Size specifier (field "sz") [B,H]"><Tb></a><text> </text><text>}</text><text>, </text><text>{</text><text> </text><a link="sa_zm1" hover="First scalable vector register of a multi-vector sequence (field Zm)"><Zm1></a><text>.</text><a link="sa_tb" hover="Size specifier (field "sz") [B,H]"><Tb></a><text>-</text><a link="sa_zm2" hover="Second scalable vector register of a multi-vector sequence (field Zm)"><Zm2></a><text>.</text><a link="sa_tb" hover="Size specifier (field "sz") [B,H]"><Tb></a><text> </text><text>}</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="UMLSLL-ZA.ZZW-2x2" mylink="UMLSLL-ZA.ZZW-2x2" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
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if sz == '1' && !<a link="impl-aarch64.HaveSMEI16I64.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEI16I64()">HaveSMEI16I64</a>() then UNDEFINED;
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constant integer esize = 32 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
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integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn:'0');
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm:'0');
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integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(o1:'00');
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constant integer nreg = 2;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Four ZA quad-vectors" oneof="2" id="iclass_sme_vgx4_quad" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="UMLSLL" />
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<docvar key="sme-multireg" value="sme-vgx4-quad" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
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</arch_variants>
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<regdiagram form="32" psname="UMLSLL-ZA.ZZW-4x4" tworows="1">
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<box hibit="31" width="9" settings="9">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="22" name="sz" usename="1">
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<c></c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="3" name="Zm" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="17" width="3" settings="3">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="14" width="2" name="Rv" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="12" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="9" width="3" name="Zn" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="6" width="2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="4" name="U" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" name="S" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="2" name="op" settings="1">
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<c>0</c>
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</box>
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<box hibit="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="0" name="o1" usename="1">
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<c></c>
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</box>
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</regdiagram>
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<encoding name="umlsll_za_zzw_4x4" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="UMLSLL" />
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<docvar key="sme-multireg" value="sme-vgx4-quad" />
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</docvars>
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<asmtemplate><text>UMLSLL ZA.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offsf" hover="Vector select offset, pointing to first of four consecutive vectors, encoded as "o1" field times 4 (field o1)"><offsf></a><text>:</text><a link="sa_offsl" hover="Vector select offset, pointing to last of four consecutive vectors, encoded as "o1" field times 4 plus 3 (field o1)"><offsl></a><a>{, VGx4}</a><text>], </text><text>{</text><text> </text><a link="sa_zn1_1" hover="First scalable vector register of a multi-vector sequence (field Zn)"><Zn1></a><text>.</text><a link="sa_tb" hover="Size specifier (field "sz") [B,H]"><Tb></a><text>-</text><a link="sa_zn4" hover="Fourth scalable vector register of a multi-vector sequence (field Zn)"><Zn4></a><text>.</text><a link="sa_tb" hover="Size specifier (field "sz") [B,H]"><Tb></a><text> </text><text>}</text><text>, </text><text>{</text><text> </text><a link="sa_zm1_1" hover="First scalable vector register of a multi-vector sequence (field Zm)"><Zm1></a><text>.</text><a link="sa_tb" hover="Size specifier (field "sz") [B,H]"><Tb></a><text>-</text><a link="sa_zm4" hover="Fourth scalable vector register of a multi-vector sequence (field Zm)"><Zm4></a><text>.</text><a link="sa_tb" hover="Size specifier (field "sz") [B,H]"><Tb></a><text> </text><text>}</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="UMLSLL-ZA.ZZW-4x4" mylink="UMLSLL-ZA.ZZW-4x4" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
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if sz == '1' && !<a link="impl-aarch64.HaveSMEI16I64.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEI16I64()">HaveSMEI16I64</a>() then UNDEFINED;
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constant integer esize = 32 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
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integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn:'00');
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm:'00');
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integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(o1:'00');
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constant integer nreg = 4;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="umlsll_za_zzw_2x2, umlsll_za_zzw_4x4" symboldefcount="1">
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<symbol link="sa_t"><T></symbol>
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<definition encodedin="sz">
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<intro>Is the size specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">sz</entry>
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<entry class="symbol"><T></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">S</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">D</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="umlsll_za_zzw_2x2, umlsll_za_zzw_4x4" symboldefcount="1">
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<symbol link="sa_wv"><Wv></symbol>
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<account encodedin="Rv">
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<intro>
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<para>Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="umlsll_za_zzw_2x2, umlsll_za_zzw_4x4" symboldefcount="1">
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<symbol link="sa_offsf"><offsf></symbol>
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<account encodedin="o1">
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<intro>
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<para>Is the vector select offset, pointing to first of four consecutive vectors, encoded as "o1" field times 4.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="umlsll_za_zzw_2x2, umlsll_za_zzw_4x4" symboldefcount="1">
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<symbol link="sa_offsl"><offsl></symbol>
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<account encodedin="o1">
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<intro>
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<para>Is the vector select offset, pointing to last of four consecutive vectors, encoded as "o1" field times 4 plus 3.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="umlsll_za_zzw_2x2" symboldefcount="1">
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<symbol link="sa_zn1"><Zn1></symbol>
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<account encodedin="Zn">
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<docvars>
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<docvar key="sme-multireg" value="sme-vgx2-quad" />
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</docvars>
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<intro>
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<para>For the two ZA quad-vectors variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn" times 2.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="umlsll_za_zzw_4x4" symboldefcount="2">
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<symbol link="sa_zn1_1"><Zn1></symbol>
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<account encodedin="Zn">
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<docvars>
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<docvar key="sme-multireg" value="sme-vgx4-quad" />
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</docvars>
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<intro>
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<para>For the four ZA quad-vectors variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn" times 4.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="umlsll_za_zzw_2x2, umlsll_za_zzw_4x4" symboldefcount="1">
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<symbol link="sa_tb"><Tb></symbol>
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<definition encodedin="sz">
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<intro>Is the size specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">sz</entry>
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<entry class="symbol"><Tb></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">B</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">H</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="umlsll_za_zzw_4x4" symboldefcount="1">
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<symbol link="sa_zn4"><Zn4></symbol>
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<account encodedin="Zn">
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<intro>
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<para>Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zn" times 4 plus 3.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="umlsll_za_zzw_2x2" symboldefcount="1">
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<symbol link="sa_zn2"><Zn2></symbol>
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<account encodedin="Zn">
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<intro>
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<para>Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zn" times 2 plus 1.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="umlsll_za_zzw_2x2" symboldefcount="1">
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<symbol link="sa_zm1"><Zm1></symbol>
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<account encodedin="Zm">
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<docvars>
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<docvar key="sme-multireg" value="sme-vgx2-quad" />
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</docvars>
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<intro>
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<para>For the two ZA quad-vectors variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zm" times 2.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="umlsll_za_zzw_4x4" symboldefcount="2">
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<symbol link="sa_zm1_1"><Zm1></symbol>
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<account encodedin="Zm">
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<docvars>
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<docvar key="sme-multireg" value="sme-vgx4-quad" />
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</docvars>
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<intro>
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<para>For the four ZA quad-vectors variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zm" times 4.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="umlsll_za_zzw_4x4" symboldefcount="1">
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<symbol link="sa_zm4"><Zm4></symbol>
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<account encodedin="Zm">
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<intro>
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<para>Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zm" times 4 plus 3.</para>
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</intro>
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|
</account>
|
|
</explanation>
|
|
<explanation enclist="umlsll_za_zzw_2x2" symboldefcount="1">
|
|
<symbol link="sa_zm2"><Zm2></symbol>
|
|
<account encodedin="Zm">
|
|
<intro>
|
|
<para>Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zm" times 2 plus 1.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
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<ps name="UMLSLL-ZA.ZZW-2x2" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEAndZAEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
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constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
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constant integer elements = VL DIV esize;
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|
integer vectors = VL DIV 8;
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|
integer vstride = vectors DIV nreg;
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|
bits(32) vbase = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[v, 32];
|
|
integer vec = (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vbase) + offset) MOD vstride;
|
|
bits(VL) result;
|
|
vec = vec - (vec MOD 4);
|
|
|
|
for r = 0 to nreg-1
|
|
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n+r, VL];
|
|
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m+r, VL];
|
|
for i = 0 to 3
|
|
bits(VL) operand3 = <a link="impl-aarch64.ZAvector.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) ZAvector[integer index, integer width]">ZAvector</a>[vec + i, VL];
|
|
for e = 0 to elements-1
|
|
integer element1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 4 * e + i, esize DIV 4]);
|
|
integer element2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 4 * e + i, esize DIV 4]);
|
|
bits(esize) product = (element1 * element2)<esize-1:0>;
|
|
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] - product;
|
|
<a link="impl-aarch64.ZAvector.write.2" file="shared_pseudocode.xml" hover="accessor: ZAvector[integer index, integer width] = bits(width) value">ZAvector</a>[vec + i, VL] = result;
|
|
vec = vec + vstride;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|