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https://github.com/pound-emu/ballistic.git
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366 lines
18 KiB
XML
366 lines
18 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="UQRSHL_advsimd" title="UQRSHL -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="UQRSHL" />
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</docvars>
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<heading>UQRSHL</heading>
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<desc>
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<brief>
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<para>Unsigned saturating Rounding Shift Left (register)</para>
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</brief>
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<authored>
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<para>Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.</para>
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<para>If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see <xref linkend="A64.instructions.UQSHL_advsimd_imm">UQSHL</xref>.</para>
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<para>If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit <xref linkend="AArch64.fpsr">FPSR</xref>.QC is set.</para>
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<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from 2 classes:</txt>
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<a href="#iclass_sisd">Scalar</a>
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<txt> and </txt>
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<a href="#iclass_simd">Vector</a>
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</classesintro>
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<iclass name="Scalar" oneof="2" id="iclass_sisd" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-type" value="sisd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="UQRSHL" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/binary/uniform/shift/sisd" tworows="1">
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<box hibit="31" width="2" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="29" name="U" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Rm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="3" name="opcode[4:2]" settings="3">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="12" name="R" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="11" name="S" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="10" settings="1">
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<c>1</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="UQRSHL_asisdsame_only" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="advsimd-type" value="sisd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="UQRSHL" />
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</docvars>
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<asmtemplate><text>UQRSHL </text><a link="sa_v" hover="Width specifier (field "size") [B,D,H,S]"><V></a><a link="sa_d" hover="SIMD&FP destination register number (field "Rd")"><d></a><text>, </text><a link="sa_v" hover="Width specifier (field "size") [B,D,H,S]"><V></a><a link="sa_n" hover="First SIMD&FP source register number (field "Rn")"><n></a><text>, </text><a link="sa_v" hover="Width specifier (field "size") [B,D,H,S]"><V></a><a link="sa_m" hover="Second SIMD&FP source register number (field "Rm")"><m></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/arithmetic/binary/uniform/shift/sisd" mylink="aarch64.instrs.vector.arithmetic.binary.uniform.shift.sisd" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
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integer datasize = esize;
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integer elements = 1;
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boolean unsigned = (U == '1');
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boolean rounding = (R == '1');
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boolean saturating = (S == '1');
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if S == '0' && size != '11' then UNDEFINED;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Vector" oneof="2" id="iclass_simd" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-reguse" value="3reg-same" />
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<docvar key="advsimd-type" value="simd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="UQRSHL" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/binary/uniform/shift/simd" tworows="1">
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<box hibit="31" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="29" name="U" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Rm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="3" name="opcode[4:2]" settings="3">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="12" name="R" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="11" name="S" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="10" settings="1">
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<c>1</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="UQRSHL_asimdsame_only" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="advsimd-reguse" value="3reg-same" />
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<docvar key="advsimd-type" value="simd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="UQRSHL" />
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</docvars>
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<asmtemplate><text>UQRSHL </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [2D,2S,4H,4S,8B,8H,16B]"><T></a><text>, </text><a link="sa_vn" hover="First SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [2D,2S,4H,4S,8B,8H,16B]"><T></a><text>, </text><a link="sa_vm" hover="Second SIMD&FP source register (field "Rm")"><Vm></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [2D,2S,4H,4S,8B,8H,16B]"><T></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/arithmetic/binary/uniform/shift/simd" mylink="aarch64.instrs.vector.arithmetic.binary.uniform.shift.simd" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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if size:Q == '110' then UNDEFINED;
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integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
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integer datasize = if Q == '1' then 128 else 64;
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integer elements = datasize DIV esize;
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boolean unsigned = (U == '1');
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boolean rounding = (R == '1');
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boolean saturating = (S == '1');</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="UQRSHL_asisdsame_only" symboldefcount="1">
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<symbol link="sa_v"><V></symbol>
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<definition encodedin="size">
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<intro>Is a width specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">size</entry>
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<entry class="symbol"><V></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="symbol">B</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="symbol">H</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="symbol">S</entry>
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</row>
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<row>
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<entry class="bitfield">11</entry>
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<entry class="symbol">D</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="UQRSHL_asisdsame_only" symboldefcount="1">
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<symbol link="sa_d"><d></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the number of the SIMD&FP destination register, in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="UQRSHL_asisdsame_only" symboldefcount="1">
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<symbol link="sa_n"><n></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the number of the first SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="UQRSHL_asisdsame_only" symboldefcount="1">
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<symbol link="sa_m"><m></symbol>
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<account encodedin="Rm">
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<intro>
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<para>Is the number of the second SIMD&FP source register, encoded in the "Rm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="UQRSHL_asimdsame_only" symboldefcount="1">
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<symbol link="sa_vd"><Vd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="UQRSHL_asimdsame_only" symboldefcount="1">
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<symbol link="sa_t"><T></symbol>
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<definition encodedin="size:Q">
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<intro>Is an arrangement specifier, </intro>
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<table class="valuetable">
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<tgroup cols="3">
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<thead>
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<row>
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<entry class="bitfield">size</entry>
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<entry class="bitfield">Q</entry>
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<entry class="symbol"><T></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">8B</entry>
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</row>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">16B</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">4H</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">8H</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">2S</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">4S</entry>
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</row>
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<row>
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<entry class="bitfield">11</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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<row>
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<entry class="bitfield">11</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">2D</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="UQRSHL_asimdsame_only" symboldefcount="1">
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<symbol link="sa_vn"><Vn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the name of the first SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="UQRSHL_asimdsame_only" symboldefcount="1">
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<symbol link="sa_vm"><Vm></symbol>
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<account encodedin="Rm">
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<intro>
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<para>Is the name of the second SIMD&FP source register, encoded in the "Rm" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/arithmetic/binary/uniform/shift/sisd" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
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bits(datasize) operand1 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
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bits(datasize) operand2 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, datasize];
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bits(datasize) result;
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boolean sat;
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for e = 0 to elements-1
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integer element = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
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integer shift = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]<7:0>);
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if shift >= 0 then // left shift
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element = element << shift;
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else // right shift
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shift = -shift;
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if rounding then
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element = (element + (1 << (shift - 1))) >> shift;
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else
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element = element >> shift;
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if saturating then
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(<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize], sat) = <a link="impl-shared.SatQ.3" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
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if sat then FPSR.QC = '1';
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else
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element<esize-1:0>;
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<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, datasize] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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