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archived-ballistic/spec/arm64_xml/whilege_pp_rr.xml
Ronald Caesar 26a677f8b4 decoder: Add ARM specification docs 
Signed-off-by: Ronald Caesar <github43132@proton.me>
2025-12-12 18:11:36 -04:00

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<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<instructionsection id="whilege_pp_rr" title="WHILEGE (predicate pair)" type="instruction">
<docvars>
<docvar key="instr-class" value="sve2" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="WHILEGE" />
<docvar key="sve-elem-type" value="8-64-elem" />
</docvars>
<heading>WHILEGE (predicate pair)</heading>
<desc>
<brief>While decrementing signed scalar greater than or equal to scalar (pair of predicates)</brief>
<description>
<para>Generate a pair of predicates that starting from the highest numbered element of the pair is true while the decrementing value of the first, signed scalar operand is greater than or equal to the second scalar operand and false thereafter down to the lowest numbered element of the pair.</para>
<para>If the second scalar operand is equal to the minimum signed integer value then a condition which includes an equality test can never fail and the result will be an all-true predicate.</para>
<para>The full width of the scalar operands is significant for the purposes of comparison, and the full width first operand is decremented by one for each destination predicate element, irrespective of the predicate result element size. The first general-purpose source register is not itself updated.</para>
<para>The lower-numbered elements are placed in the first predicate destination register, and the higher-numbered elements in the second predicate destination register. Sets the <arm-defined-word>First</arm-defined-word> (N), <arm-defined-word>None</arm-defined-word> (Z), <arm-defined-word>!Last</arm-defined-word> (C) condition flags based on the predicate result, and the V flag to zero.</para>
</description>
<status>Green</status>
<predicated>False</predicated>
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
</desc>
<alias_list howmany="0"></alias_list>
<classes>
<iclass name="SVE2" oneof="1" id="iclass_sve2" no_encodings="1" isa="A64">
<docvars>
<docvar key="instr-class" value="sve2" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="WHILEGE" />
<docvar key="sve-elem-type" value="8-64-elem" />
</docvars>
<iclassintro count="1"></iclassintro>
<arch_variants>
<arch_variant name="FEAT_SVE2p1" feature="FEAT_SVE2p1" />
</arch_variants>
<regdiagram form="32" psname="WHILEGE-PP.RR-_" tworows="1">
<box hibit="31" width="8" settings="8">
<c>0</c>
<c>0</c>
<c>1</c>
<c>0</c>
<c>0</c>
<c>1</c>
<c>0</c>
<c>1</c>
</box>
<box hibit="23" width="2" name="size" usename="1">
<c colspan="2"></c>
</box>
<box hibit="21" settings="1">
<c>1</c>
</box>
<box hibit="20" width="5" name="Rm" usename="1">
<c colspan="5"></c>
</box>
<box hibit="15" width="4" settings="4">
<c>0</c>
<c>1</c>
<c>0</c>
<c>1</c>
</box>
<box hibit="11" name="U" usename="1" settings="1">
<c>0</c>
</box>
<box hibit="10" name="lt" usename="1" settings="1">
<c>0</c>
</box>
<box hibit="9" width="5" name="Rn" usename="1">
<c colspan="5"></c>
</box>
<box hibit="4" settings="1">
<c>1</c>
</box>
<box hibit="3" width="3" name="Pd" usename="1">
<c colspan="3"></c>
</box>
<box hibit="0" name="eq" usename="1" settings="1">
<c>0</c>
</box>
</regdiagram>
<encoding name="whilege_pp_rr_" oneofinclass="1" oneof="1" label="">
<docvars>
<docvar key="instr-class" value="sve2" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="WHILEGE" />
<docvar key="sve-elem-type" value="8-64-elem" />
</docvars>
<asmtemplate><text>WHILEGE </text><text>{</text><text> </text><a link="sa_pd1" hover="First destination scalable predicate register (field Pd)">&lt;Pd1&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [B,D,H,S]">&lt;T&gt;</a><text>, </text><a link="sa_pd2" hover="Second destination scalable predicate register (field Pd)">&lt;Pd2&gt;</a><text>.</text><a link="sa_t" hover="Size specifier (field &quot;size&quot;) [B,D,H,S]">&lt;T&gt;</a><text> </text><text>}</text><text>, </text><a link="sa_xn" hover="First 64-bit source general-purpose register (field &quot;Rn&quot;)">&lt;Xn&gt;</a><text>, </text><a link="sa_xm" hover="Second 64-bit source general-purpose register (field &quot;Rm&quot;)">&lt;Xm&gt;</a></asmtemplate>
</encoding>
<ps_section howmany="1">
<ps name="WHILEGE-PP.RR-_" mylink="WHILEGE-PP.RR-_" enclabels="" sections="1" secttype="noheading">
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() &amp;&amp; !<a link="impl-aarch64.HaveSVE2p1.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2p1()">HaveSVE2p1</a>() then UNDEFINED;
constant integer esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
constant integer rsize = 64;
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
integer d0 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pd:'0');
integer d1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pd:'1');
boolean unsigned = FALSE;
<a link="SVECmp" file="shared_pseudocode.xml" hover="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a link="Cmp_GE" file="shared_pseudocode.xml" hover="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GE</a>;</pstext>
</ps>
</ps_section>
</iclass>
</classes>
<explanations scope="all">
<explanation enclist="whilege_pp_rr_" symboldefcount="1">
<symbol link="sa_pd1">&lt;Pd1&gt;</symbol>
<account encodedin="Pd">
<intro>
<para>Is the name of the first destination scalable predicate register, encoded as "Pd" times 2.</para>
</intro>
</account>
</explanation>
<explanation enclist="whilege_pp_rr_" symboldefcount="1">
<symbol link="sa_t">&lt;T&gt;</symbol>
<definition encodedin="size">
<intro>Is the size specifier, </intro>
<table class="valuetable">
<tgroup cols="2">
<thead>
<row>
<entry class="bitfield">size</entry>
<entry class="symbol">&lt;T&gt;</entry>
</row>
</thead>
<tbody>
<row>
<entry class="bitfield">00</entry>
<entry class="symbol">B</entry>
</row>
<row>
<entry class="bitfield">01</entry>
<entry class="symbol">H</entry>
</row>
<row>
<entry class="bitfield">10</entry>
<entry class="symbol">S</entry>
</row>
<row>
<entry class="bitfield">11</entry>
<entry class="symbol">D</entry>
</row>
</tbody>
</tgroup>
</table>
</definition>
</explanation>
<explanation enclist="whilege_pp_rr_" symboldefcount="1">
<symbol link="sa_pd2">&lt;Pd2&gt;</symbol>
<account encodedin="Pd">
<intro>
<para>Is the name of the second destination scalable predicate register, encoded as "Pd" times 2 plus 1.</para>
</intro>
</account>
</explanation>
<explanation enclist="whilege_pp_rr_" symboldefcount="1">
<symbol link="sa_xn">&lt;Xn&gt;</symbol>
<account encodedin="Rn">
<intro>
<para>Is the 64-bit name of the first source general-purpose register, encoded in the "Rn" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="whilege_pp_rr_" symboldefcount="1">
<symbol link="sa_xm">&lt;Xm&gt;</symbol>
<account encodedin="Rm">
<intro>
<para>Is the 64-bit name of the second source general-purpose register, encoded in the "Rm" field.</para>
</intro>
</account>
</explanation>
</explanations>
<ps_section howmany="1">
<ps name="WHILEGE-PP.RR-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL*2) mask = <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(PL*2);
bits(rsize) operand1 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, rsize];
bits(rsize) operand2 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[m, rsize];
bits(PL*2) result;
boolean last = TRUE;
constant integer psize = esize DIV 8;
for e = (elements*2)-1 downto 0
boolean cond;
case op of
when <a link="Cmp_GT" file="shared_pseudocode.xml" hover="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GT</a> cond = (<a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(operand1, unsigned) &gt; <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(operand2, unsigned));
when <a link="Cmp_GE" file="shared_pseudocode.xml" hover="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GE</a> cond = (<a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(operand1, unsigned) &gt;= <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(operand2, unsigned));
last = last &amp;&amp; cond;
bit pbit = if last then '1' else '0';
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, psize] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(pbit, psize);
operand1 = operand1 - 1;
PSTATE.&lt;N,Z,C,V&gt; = <a link="impl-aarch64.PredTest.3" file="shared_pseudocode.xml" hover="function: bits(4) PredTest(bits(N) mask, bits(N) result, integer esize)">PredTest</a>(mask, result, esize);
<a link="impl-aarch64.P.write.2" file="shared_pseudocode.xml" hover="accessor: P[integer n, integer width] = bits(width) value">P</a>[d0, PL] = result&lt;PL-1:0&gt;;
<a link="impl-aarch64.P.write.2" file="shared_pseudocode.xml" hover="accessor: P[integer n, integer width] = bits(width) value">P</a>[d1, PL] = result&lt;PL*2-1:PL&gt;;</pstext>
</ps>
</ps_section>
</instructionsection>
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