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https://github.com/pound-emu/ballistic.git
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212 lines
13 KiB
XML
212 lines
13 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="RCWSET" title="RCWSET, RCWSETA, RCWSETL, RCWSETAL -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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</docvars>
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<heading>RCWSET, RCWSETA, RCWSETL, RCWSETAL</heading>
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<desc>
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<brief>
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<para>Read Check Write atomic bit Set on doubleword in memory</para>
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</brief>
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<authored>
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<para>Read Check Write atomic bit Set on doubleword in memory atomically loads a 64-bit doubleword from memory, performs a bitwise OR with the complement of the value held in a register on it, and conditionally stores the result back to memory. Storing of the result back to memory is conditional on RCW Checks. The value initially loaded from memory is returned in the destination register. This instruction updates the condition flags based on the result of the update of memory.</para>
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<list type="unordered">
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<listitem><content><instruction>RCWSETA</instruction> and <instruction>RCWSETAL</instruction> load from memory with acquire semantics.</content></listitem>
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<listitem><content><instruction>RCWSETL</instruction> and <instruction>RCWSETAL</instruction> store to memory with release semantics.</content></listitem>
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<listitem><content><instruction>RCWSET</instruction> has neither acquire nor release semantics.</content></listitem>
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</list>
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</authored>
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</desc>
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<operationalnotes>
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<para>If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Integer" oneof="1" id="iclass_general" no_encodings="4" isa="A64">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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</docvars>
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<iclassintro count="4"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.9" feature="FEAT_THE" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/memory/rcw/ld/rcwset" tworows="1">
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<box hibit="31" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="S" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="29" width="3" settings="3">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="26" name="V" settings="1">
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<c>0</c>
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</box>
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<box hibit="25" width="2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" name="A" usename="1">
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<c></c>
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</box>
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<box hibit="22" name="R" usename="1">
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<c></c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Rs" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" name="o3" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="14" width="3" name="opc" usename="1" settings="3" psbits="xxx">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="RCWSET_64_memop" oneofinclass="4" oneof="4" label="RCWSET" bitdiffs="A == 0 && R == 0">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="RCWSET" />
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</docvars>
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<box hibit="23" width="1" name="A">
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<c>0</c>
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</box>
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<box hibit="22" width="1" name="R">
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<c>0</c>
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</box>
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<asmtemplate><text>RCWSET </text><a link="sa_xs" hover="64-bit general-purpose register to be stored (field "Rs")"><Xs></a><text>, </text><a link="sa_xt" hover="64-bit general-purpose register to be loaded (field "Rt")"><Xt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>]</text></asmtemplate>
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</encoding>
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<encoding name="RCWSETA_64_memop" oneofinclass="4" oneof="4" label="RCWSETA" bitdiffs="A == 1 && R == 0">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="RCWSETA" />
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</docvars>
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<box hibit="23" width="1" name="A">
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<c>1</c>
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</box>
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<box hibit="22" width="1" name="R">
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<c>0</c>
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</box>
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<asmtemplate><text>RCWSETA </text><a link="sa_xs" hover="64-bit general-purpose register to be stored (field "Rs")"><Xs></a><text>, </text><a link="sa_xt" hover="64-bit general-purpose register to be loaded (field "Rt")"><Xt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>]</text></asmtemplate>
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</encoding>
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<encoding name="RCWSETAL_64_memop" oneofinclass="4" oneof="4" label="RCWSETAL" bitdiffs="A == 1 && R == 1">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="RCWSETAL" />
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</docvars>
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<box hibit="23" width="1" name="A">
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<c>1</c>
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</box>
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<box hibit="22" width="1" name="R">
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<c>1</c>
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</box>
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<asmtemplate><text>RCWSETAL </text><a link="sa_xs" hover="64-bit general-purpose register to be stored (field "Rs")"><Xs></a><text>, </text><a link="sa_xt" hover="64-bit general-purpose register to be loaded (field "Rt")"><Xt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>]</text></asmtemplate>
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</encoding>
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<encoding name="RCWSETL_64_memop" oneofinclass="4" oneof="4" label="RCWSETL" bitdiffs="A == 0 && R == 1">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="RCWSETL" />
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</docvars>
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<box hibit="23" width="1" name="A">
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<c>0</c>
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</box>
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<box hibit="22" width="1" name="R">
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<c>1</c>
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</box>
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<asmtemplate><text>RCWSETL </text><a link="sa_xs" hover="64-bit general-purpose register to be stored (field "Rs")"><Xs></a><text>, </text><a link="sa_xt" hover="64-bit general-purpose register to be loaded (field "Rt")"><Xt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/rcw/ld/rcwset" mylink="aarch64.instrs.memory.rcw.ld.rcwset" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveTHExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTHExt()">HaveTHExt</a>() then UNDEFINED;
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);
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boolean soft = FALSE;
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boolean acquire = A == '1' && Rt != '11111';
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boolean release = R == '1';
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<a link="MemAtomicOp" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp</a> op = if opc == '001' then <a link="MemAtomicOp_BIC" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_BIC</a> else <a link="MemAtomicOp_ORR" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_ORR</a>;
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boolean tagchecked = n != 31;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="RCWSET_64_memop, RCWSETA_64_memop, RCWSETL_64_memop, RCWSETAL_64_memop" symboldefcount="1">
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<symbol link="sa_xs"><Xs></symbol>
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<account encodedin="Rs">
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<intro>
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<para>Is the 64-bit name of the general-purpose register to be stored, encoded in the "Rs" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="RCWSET_64_memop, RCWSETA_64_memop, RCWSETL_64_memop, RCWSETAL_64_memop" symboldefcount="1">
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<symbol link="sa_xt"><Xt></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="RCWSET_64_memop, RCWSETA_64_memop, RCWSETL_64_memop, RCWSETAL_64_memop" symboldefcount="1">
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<symbol link="sa_xn_sp"><Xn|SP></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/rcw/ld/rcwset" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch64.IsD128Enabled.1" file="shared_pseudocode.xml" hover="function: boolean IsD128Enabled(bits(2) el)">IsD128Enabled</a>(PSTATE.EL) then UNDEFINED;
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bits(64) address;
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bits(64) newdata = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[s, 64];
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bits(64) readdata;
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bits(4) nzcv;
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<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescRCW.5" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescRCW(MemAtomicOp modop, boolean soft, boolean acquire, boolean release, boolean tagchecked)">CreateAccDescRCW</a>(op, soft, acquire, release, tagchecked);
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if n == 31 then
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<a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
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address = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
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else
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address = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
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bits(64) compdata = bits(64) UNKNOWN; // Irrelevant when not executing CAS
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(nzcv, readdata) = <a link="impl-aarch64.MemAtomicRCW.4" file="shared_pseudocode.xml" hover="function: (bits(4), bits(size)) MemAtomicRCW(bits(64) address, bits(size) cmpoperand, bits(size) operand, AccessDescriptor accdesc_in)">MemAtomicRCW</a>(address, compdata, newdata, accdesc);
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PSTATE.<N,Z,C,V> = nzcv;
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<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[t, 64] = readdata; // Return the old value when t!=31</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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