mirror of
https://github.com/pound-emu/ballistic.git
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149 lines
7.8 KiB
XML
149 lines
7.8 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="ST64B" title="ST64B -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ST64B" />
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</docvars>
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<heading>ST64B</heading>
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<desc>
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<brief>
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<para>Single-copy Atomic 64-byte Store without Return</para>
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</brief>
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<authored>
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<para>Single-copy Atomic 64-byte Store without Return stores eight 64-bit doublewords from consecutive registers, <syntax>Xt</syntax> to <syntax>X(t+7)</syntax>, to a memory location. The data that is stored is atomic and is required to be 64-byte-aligned.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Integer" oneof="1" id="iclass_general" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ST64B" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.7" feature="FEAT_LS64" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/memory/atomicops/st_acc/st64b">
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<box hibit="31" width="2" name="size" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="29" width="3" settings="3">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="26" name="V" settings="1">
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<c>0</c>
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</box>
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<box hibit="25" width="2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" name="A" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" name="R" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Rs" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="15" name="o3" settings="1">
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<c>1</c>
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</box>
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<box hibit="14" width="3" name="opc" settings="3">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="ST64B_64L_memop" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ST64B" />
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</docvars>
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<asmtemplate><text>ST64B </text><a link="sa_xt" hover="First 64-bit general-purpose register to be transferred (field "Rt")"><Xt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text> {,#0}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/atomicops/st_acc/st64b" mylink="aarch64.instrs.memory.atomicops.st_acc.st64b" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFeatLS64.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatLS64()">HaveFeatLS64</a>() then UNDEFINED;
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if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
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<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop = <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;
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boolean tagchecked = n != 31;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="ST64B_64L_memop" symboldefcount="1">
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<symbol link="sa_xt"><Xt></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ST64B_64L_memop" symboldefcount="1">
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<symbol link="sa_xn_sp"><Xn|SP></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/atomicops/st_acc/st64b" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckLDST64BEnabled.0" file="shared_pseudocode.xml" hover="function: CheckLDST64BEnabled()">CheckLDST64BEnabled</a>();
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bits(512) data;
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bits(64) address;
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bits(64) value;
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<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescLS64.2" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescLS64(MemOp memop, boolean tagchecked)">CreateAccDescLS64</a>(memop, tagchecked);
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for i = 0 to 7
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value = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[t+i, 64];
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if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then value = <a link="impl-shared.BigEndianReverse.1" file="shared_pseudocode.xml" hover="function: bits(width) BigEndianReverse (bits(width) value)">BigEndianReverse</a>(value);
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data<63+64*i : 64*i> = value;
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if n == 31 then
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<a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
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address = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
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else
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address = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
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<a link="impl-aarch64.MemStore64B.3" file="shared_pseudocode.xml" hover="function: MemStore64B(bits(64) address, bits(512) value, AccessDescriptor accdesc_in)">MemStore64B</a>(address, data, accdesc);</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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