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https://github.com/pound-emu/ballistic.git
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257 lines
14 KiB
XML
257 lines
14 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="AND_log_shift" title="AND (shifted register) -- A64" type="instruction">
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<docvars>
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<docvar key="cond-setting" value="no-s" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="AND" />
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<docvar key="reguse" value="shifted-reg" />
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</docvars>
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<heading>AND (shifted register)</heading>
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<desc>
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<brief>
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<para>Bitwise AND (shifted register)</para>
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</brief>
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<authored>
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<para>Bitwise AND (shifted register) performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register.</para>
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</authored>
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</desc>
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<operationalnotes>
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<para>If PSTATE.DIT is 1:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Not setting the condition flags" oneof="1" id="iclass_no_s" no_encodings="2" isa="A64">
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<docvars>
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<docvar key="cond-setting" value="no-s" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="AND" />
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<docvar key="reguse" value="shifted-reg" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/integer/logical/shiftedreg" tworows="1">
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<box hibit="31" name="sf" usename="1">
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<c></c>
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</box>
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<box hibit="30" width="2" name="opc" usename="1" settings="2" psbits="xx">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" width="2" name="shift" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="21" name="N" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="20" width="5" name="Rm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="6" name="imm6" usename="1">
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<c colspan="6"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="AND_32_log_shift" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
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<docvars>
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<docvar key="cond-setting" value="no-s" />
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<docvar key="datatype" value="32" />
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<docvar key="datatype-reguse" value="32-shifted-reg" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="AND" />
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<docvar key="reguse" value="shifted-reg" />
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</docvars>
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<box hibit="31" width="1" name="sf">
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<c>0</c>
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</box>
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<asmtemplate><text>AND </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_wn" hover="First 32-bit general-purpose source register (field "Rn")"><Wn></a><text>, </text><a link="sa_wm" hover="Second 32-bit general-purpose source register (field "Rm")"><Wm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional shift applied to final source, default LSL (field "shift") [ASR,LSL,LSR,ROR]"><shift></a><text> #</text><a link="sa_amount" hover="Shift amount [0-31], default 0 (field "imm6")"><amount></a><text>}</text></asmtemplate>
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</encoding>
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<encoding name="AND_64_log_shift" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
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<docvars>
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<docvar key="cond-setting" value="no-s" />
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<docvar key="datatype" value="64" />
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<docvar key="datatype-reguse" value="64-shifted-reg" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="AND" />
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<docvar key="reguse" value="shifted-reg" />
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</docvars>
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<box hibit="31" width="1" name="sf">
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<c>1</c>
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</box>
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<asmtemplate><text>AND </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn" hover="First 64-bit general-purpose source register (field "Rn")"><Xn></a><text>, </text><a link="sa_xm" hover="Second 64-bit general-purpose source register (field "Rm")"><Xm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional shift applied to final source, default LSL (field "shift") [ASR,LSL,LSR,ROR]"><shift></a><text> #</text><a link="sa_amount_1" hover="Shift amount [0-63], default 0 (field "imm6")"><amount></a><text>}</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/integer/logical/shiftedreg" mylink="aarch64.instrs.integer.logical.shiftedreg" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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integer datasize = if sf == '1' then 64 else 32;
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boolean setflags;
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<a link="LogicalOp" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp</a> op;
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case opc of
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when '00' op = <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a>; setflags = FALSE;
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when '01' op = <a link="LogicalOp_ORR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_ORR</a>; setflags = FALSE;
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when '10' op = <a link="LogicalOp_EOR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_EOR</a>; setflags = FALSE;
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when '11' op = <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a>; setflags = TRUE;
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if sf == '0' && imm6<5> == '1' then UNDEFINED;
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<a link="ShiftType" file="shared_pseudocode.xml" hover="enumeration ShiftType {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType</a> shift_type = <a link="impl-aarch64.DecodeShift.1" file="shared_pseudocode.xml" hover="function: ShiftType DecodeShift(bits(2) op)">DecodeShift</a>(shift);
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integer shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);
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boolean invert = (N == '1');</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="AND_32_log_shift" symboldefcount="1">
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<symbol link="sa_wd"><Wd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="AND_32_log_shift" symboldefcount="1">
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<symbol link="sa_wn"><Wn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="AND_32_log_shift" symboldefcount="1">
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<symbol link="sa_wm"><Wm></symbol>
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<account encodedin="Rm">
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<intro>
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<para>Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="AND_64_log_shift" symboldefcount="1">
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<symbol link="sa_xd"><Xd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="AND_64_log_shift" symboldefcount="1">
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<symbol link="sa_xn"><Xn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="AND_64_log_shift" symboldefcount="1">
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<symbol link="sa_xm"><Xm></symbol>
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<account encodedin="Rm">
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<intro>
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<para>Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="AND_32_log_shift, AND_64_log_shift" symboldefcount="1">
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<symbol link="sa_shift"><shift></symbol>
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<definition encodedin="shift">
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<intro>Is the optional shift to be applied to the final source, defaulting to LSL and </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">shift</entry>
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<entry class="symbol"><shift></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="symbol">LSL</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="symbol">LSR</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="symbol">ASR</entry>
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</row>
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<row>
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<entry class="bitfield">11</entry>
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<entry class="symbol">ROR</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="AND_32_log_shift" symboldefcount="1">
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<symbol link="sa_amount"><amount></symbol>
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<account encodedin="imm6">
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<docvars>
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<docvar key="datatype" value="32" />
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<docvar key="datatype-reguse" value="32-shifted-reg" />
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</docvars>
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<intro>
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<para>For the 32-bit variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="AND_64_log_shift" symboldefcount="2">
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<symbol link="sa_amount_1"><amount></symbol>
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<account encodedin="imm6">
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<docvars>
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<docvar key="datatype" value="64" />
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<docvar key="datatype-reguse" value="64-shifted-reg" />
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</docvars>
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<intro>
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<para>For the 64-bit variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field,</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/integer/logical/shiftedreg" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(datasize) operand1 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, datasize];
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bits(datasize) operand2 = <a link="impl-aarch64.ShiftReg.4" file="shared_pseudocode.xml" hover="function: bits(N) ShiftReg(integer reg, ShiftType shiftype, integer amount, integer N)">ShiftReg</a>(m, shift_type, shift_amount, datasize);
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bits(datasize) result;
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if invert then operand2 = NOT(operand2);
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case op of
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when <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a> result = operand1 AND operand2;
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when <a link="LogicalOp_ORR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_ORR</a> result = operand1 OR operand2;
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when <a link="LogicalOp_EOR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_EOR</a> result = operand1 EOR operand2;
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if setflags then
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PSTATE.<N,Z,C,V> = result<datasize-1>:<a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result):'00';
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<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, datasize] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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