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302 lines
17 KiB
XML
302 lines
17 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="bfmla_za_zzi" title="BFMLA (multiple and indexed vector)" type="instruction">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="BFMLA" />
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</docvars>
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<heading>BFMLA (multiple and indexed vector)</heading>
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<desc>
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<brief>Multi-vector BFloat16 floating-point fused multiply-add by indexed element</brief>
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<description>
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<para>The instruction operates on two or four ZA single-vector groups.</para>
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<para>Multiply the indexed element of the second source vector by the corresponding BFloat16 floating-point elements of the two or four first source vectors and destructively add without intermediate rounding to the corresponding elements of the two or four ZA single-vector groups.</para>
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<para>The elements within the second source vector are specified using an immediate element index which selects the same element position within each 128-bit vector segment. The index range is from 0 to 7, encoded in 3 bits. The vector numbers forming the single-vector group within each half or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo half or quarter the number of ZA array vectors.</para>
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<para>The <arm-defined-word>vector group</arm-defined-word> symbol, <syntax>VGx2</syntax> or <syntax>VGx4</syntax>, indicates that the ZA operand consists of two or four ZA single-vector groups respectively. The <arm-defined-word>vector group</arm-defined-word> symbol is preferred for disassembly, but optional in assembler source code.</para>
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<para>This instruction follows SME2.1 ZA-targeting non-widening BFloat16 numerical behaviors.</para>
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<para>This instruction is unpredicated.</para>
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<para>ID_AA64SMFR0_EL1.B16B16 indicates whether this instruction is implemented.</para>
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</description>
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<status>Green</status>
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<predicated>False</predicated>
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<sm_policy>SM_1_only</sm_policy>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from 2 classes:</txt>
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<a href="#iclass_sme_vgx2_single">Two ZA single-vectors</a>
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<txt> and </txt>
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<a href="#iclass_sme_vgx4_single">Four ZA single-vectors</a>
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</classesintro>
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<iclass name="Two ZA single-vectors" oneof="2" id="iclass_sme_vgx2_single" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="BFMLA" />
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<docvar key="sme-multireg" value="sme-vgx2-single" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="FEAT_B16B16" feature="FEAT_B16B16" />
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</arch_variants>
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<regdiagram form="32" psname="BFMLA-ZA.ZZi-H2xi" tworows="1">
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<box hibit="31" width="12" settings="12">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Zm" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" settings="1">
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<c>0</c>
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</box>
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<box hibit="14" width="2" name="Rv" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="12" settings="1">
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<c>1</c>
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</box>
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<box hibit="11" width="2" name="i3h" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="9" width="4" name="Zn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="5" name="op" settings="1">
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<c>1</c>
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</box>
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<box hibit="4" name="S" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" name="i3l" usename="1">
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<c></c>
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</box>
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<box hibit="2" width="3" name="off3" usename="1">
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<c colspan="3"></c>
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</box>
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</regdiagram>
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<encoding name="bfmla_za_zzi_h2xi" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="BFMLA" />
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<docvar key="sme-multireg" value="sme-vgx2-single" />
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</docvars>
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<asmtemplate><text>BFMLA ZA.H[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offs" hover="Vector select offset [0-7] (field "off3")"><offs></a><a>{, VGx2}</a><text>], </text><text>{</text><text> </text><a link="sa_zn1" hover="First scalable vector register of a multi-vector sequence (field Zn)"><Zn1></a><text>.H-</text><a link="sa_zn2" hover="Second scalable vector register of a multi-vector sequence (field Zn)"><Zn2></a><text>.H </text><text>}</text><text>, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field "Zm")"><Zm></a><text>.H[</text><a link="sa_index" hover="Element index [0-7] (field "i3h:i3l")"><index></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="BFMLA-ZA.ZZi-H2xi" mylink="BFMLA-ZA.ZZi-H2xi" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSMEB16B16.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEB16B16()">HaveSMEB16B16</a>() then UNDEFINED;
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integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
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constant integer esize = 16;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn:'0');
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
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integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off3);
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integer index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(i3h:i3l);
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boolean sub_op = FALSE;
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constant integer nreg = 2;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Four ZA single-vectors" oneof="2" id="iclass_sme_vgx4_single" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="BFMLA" />
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<docvar key="sme-multireg" value="sme-vgx4-single" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="FEAT_B16B16" feature="FEAT_B16B16" />
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</arch_variants>
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<regdiagram form="32" psname="BFMLA-ZA.ZZi-H4xi" tworows="1">
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<box hibit="31" width="12" settings="12">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Zm" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" settings="1">
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<c>1</c>
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</box>
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<box hibit="14" width="2" name="Rv" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="12" settings="1">
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<c>1</c>
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</box>
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<box hibit="11" width="2" name="i3h" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="9" width="3" name="Zn" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="6" settings="1">
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<c>0</c>
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</box>
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<box hibit="5" name="op" settings="1">
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<c>1</c>
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</box>
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<box hibit="4" name="S" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" name="i3l" usename="1">
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<c></c>
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</box>
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<box hibit="2" width="3" name="off3" usename="1">
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<c colspan="3"></c>
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</box>
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</regdiagram>
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<encoding name="bfmla_za_zzi_h4xi" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="BFMLA" />
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<docvar key="sme-multireg" value="sme-vgx4-single" />
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</docvars>
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<asmtemplate><text>BFMLA ZA.H[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offs" hover="Vector select offset [0-7] (field "off3")"><offs></a><a>{, VGx4}</a><text>], </text><text>{</text><text> </text><a link="sa_zn1_1" hover="First scalable vector register of a multi-vector sequence (field Zn)"><Zn1></a><text>.H-</text><a link="sa_zn4" hover="Fourth scalable vector register of a multi-vector sequence (field Zn)"><Zn4></a><text>.H </text><text>}</text><text>, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field "Zm")"><Zm></a><text>.H[</text><a link="sa_index" hover="Element index [0-7] (field "i3h:i3l")"><index></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="BFMLA-ZA.ZZi-H4xi" mylink="BFMLA-ZA.ZZi-H4xi" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSMEB16B16.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEB16B16()">HaveSMEB16B16</a>() then UNDEFINED;
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integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
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constant integer esize = 16;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn:'00');
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
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integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off3);
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integer index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(i3h:i3l);
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boolean sub_op = FALSE;
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constant integer nreg = 4;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="bfmla_za_zzi_h2xi, bfmla_za_zzi_h4xi" symboldefcount="1">
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<symbol link="sa_wv"><Wv></symbol>
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<account encodedin="Rv">
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<intro>
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<para>Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="bfmla_za_zzi_h2xi, bfmla_za_zzi_h4xi" symboldefcount="1">
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<symbol link="sa_offs"><offs></symbol>
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<account encodedin="off3">
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<intro>
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<para>Is the vector select offset, in the range 0 to 7, encoded in the "off3" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="bfmla_za_zzi_h2xi" symboldefcount="1">
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<symbol link="sa_zn1"><Zn1></symbol>
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<account encodedin="Zn">
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<docvars>
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<docvar key="sme-multireg" value="sme-vgx2-single" />
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</docvars>
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<intro>
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<para>For the two ZA single-vectors variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn" times 2.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="bfmla_za_zzi_h4xi" symboldefcount="2">
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<symbol link="sa_zn1_1"><Zn1></symbol>
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<account encodedin="Zn">
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<docvars>
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<docvar key="sme-multireg" value="sme-vgx4-single" />
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</docvars>
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<intro>
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<para>For the four ZA single-vectors variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn" times 4.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="bfmla_za_zzi_h4xi" symboldefcount="1">
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<symbol link="sa_zn4"><Zn4></symbol>
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<account encodedin="Zn">
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<intro>
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<para>Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zn" times 4 plus 3.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="bfmla_za_zzi_h2xi" symboldefcount="1">
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<symbol link="sa_zn2"><Zn2></symbol>
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<account encodedin="Zn">
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<intro>
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<para>Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zn" times 2 plus 1.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="bfmla_za_zzi_h2xi, bfmla_za_zzi_h4xi" symboldefcount="1">
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<symbol link="sa_zm"><Zm></symbol>
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<account encodedin="Zm">
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<intro>
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<para>Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="bfmla_za_zzi_h2xi, bfmla_za_zzi_h4xi" symboldefcount="1">
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<symbol link="sa_index"><index></symbol>
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<account encodedin="i3h:i3l">
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<intro>
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<para>Is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="BFMLA-ZA.ZZi-H2xi" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEAndZAEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
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constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
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constant integer elements = VL DIV 16;
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integer vectors = VL DIV 8;
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integer vstride = vectors DIV nreg;
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integer eltspersegment = 128 DIV 16;
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bits(32) vbase = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[v, 32];
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integer vec = (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vbase) + offset) MOD vstride;
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bits(VL) result;
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for r = 0 to nreg-1
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bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n+r, VL];
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bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
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bits(VL) operand3 = <a link="impl-aarch64.ZAvector.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) ZAvector[integer index, integer width]">ZAvector</a>[vec, VL];
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for e = 0 to elements-1
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bits(16) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 16];
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integer segmentbase = e - (e MOD eltspersegment);
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integer s = segmentbase + index;
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bits(16) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, s, 16];
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bits(16) element3 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 16];
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if sub_op then element1 = <a link="impl-shared.BFNeg.1" file="shared_pseudocode.xml" hover="function: bits(16) BFNeg(bits(16) op)">BFNeg</a>(element1);
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 16] = <a link="impl-shared.BFMulAdd_ZA.4" file="shared_pseudocode.xml" hover="function: bits(16) BFMulAdd_ZA(bits(16) addend, bits(16) op1, bits(16) op2, FPCRType fpcr_in)">BFMulAdd_ZA</a>(element3, element1, element2, FPCR[]);
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<a link="impl-aarch64.ZAvector.write.2" file="shared_pseudocode.xml" hover="accessor: ZAvector[integer index, integer width] = bits(width) value">ZAvector</a>[vec, VL] = result;
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vec = vec + vstride;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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