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archived-ballistic/spec/arm64_xml/eor_log_imm.xml
Ronald Caesar 26a677f8b4 decoder: Add ARM specification docs
Signed-off-by: Ronald Caesar <github43132@proton.me>
2025-12-12 18:11:36 -04:00

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<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<instructionsection id="EOR_log_imm" title="EOR (immediate) -- A64" type="instruction">
<docvars>
<docvar key="cond-setting" value="no-s" />
<docvar key="immediate-type" value="imm12-bitfield" />
<docvar key="instr-class" value="general" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="EOR" />
</docvars>
<heading>EOR (immediate)</heading>
<desc>
<brief>
<para>Bitwise Exclusive-OR (immediate)</para>
</brief>
<authored>
<para>Bitwise Exclusive-OR (immediate) performs a bitwise exclusive-OR of a register value and an immediate value, and writes the result to the destination register.</para>
</authored>
</desc>
<operationalnotes>
<para>If PSTATE.DIT is 1:</para>
<list type="unordered">
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
</list>
</operationalnotes>
<alias_list howmany="0"></alias_list>
<classes>
<iclass name="Not setting the condition flags" oneof="1" id="iclass_no_s" no_encodings="2" isa="A64">
<docvars>
<docvar key="cond-setting" value="no-s" />
<docvar key="immediate-type" value="imm12-bitfield" />
<docvar key="instr-class" value="general" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="EOR" />
</docvars>
<iclassintro count="2"></iclassintro>
<regdiagram form="32" psname="aarch64/instrs/integer/logical/immediate" tworows="1">
<box hibit="31" name="sf" usename="1">
<c></c>
</box>
<box hibit="30" width="2" name="opc" usename="1" settings="2" psbits="xx">
<c>1</c>
<c>0</c>
</box>
<box hibit="28" width="6" settings="6">
<c>1</c>
<c>0</c>
<c>0</c>
<c>1</c>
<c>0</c>
<c>0</c>
</box>
<box hibit="22" name="N" usename="1">
<c></c>
</box>
<box hibit="21" width="6" name="immr" usename="1">
<c colspan="6"></c>
</box>
<box hibit="15" width="6" name="imms" usename="1">
<c colspan="6"></c>
</box>
<box hibit="9" width="5" name="Rn" usename="1">
<c colspan="5"></c>
</box>
<box hibit="4" width="5" name="Rd" usename="1">
<c colspan="5"></c>
</box>
</regdiagram>
<encoding name="EOR_32_log_imm" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0 &amp;&amp; N == 0">
<docvars>
<docvar key="cond-setting" value="no-s" />
<docvar key="datatype" value="32" />
<docvar key="immediate-type" value="imm12-bitfield" />
<docvar key="instr-class" value="general" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="EOR" />
</docvars>
<box hibit="31" width="1" name="sf">
<c>0</c>
</box>
<box hibit="22" width="1" name="N">
<c>0</c>
</box>
<asmtemplate><text>EOR </text><a link="sa_wd_wsp" hover="32-bit destination general-purpose register or WSP (field &quot;Rd&quot;)">&lt;Wd|WSP&gt;</a><text>, </text><a link="sa_wn" hover="32-bit general-purpose source register (field &quot;Rn&quot;)">&lt;Wn&gt;</a><text>, #</text><a link="sa_imm" hover="Bitmask immediate (field &quot;imms:immr&quot;)">&lt;imm&gt;</a></asmtemplate>
</encoding>
<encoding name="EOR_64_log_imm" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
<docvars>
<docvar key="cond-setting" value="no-s" />
<docvar key="datatype" value="64" />
<docvar key="immediate-type" value="imm12-bitfield" />
<docvar key="instr-class" value="general" />
<docvar key="isa" value="A64" />
<docvar key="mnemonic" value="EOR" />
</docvars>
<box hibit="31" width="1" name="sf">
<c>1</c>
</box>
<asmtemplate><text>EOR </text><a link="sa_xd_sp" hover="64-bit destination general-purpose register or SP (field &quot;Rd&quot;)">&lt;Xd|SP&gt;</a><text>, </text><a link="sa_xn" hover="64-bit general-purpose source register (field &quot;Rn&quot;)">&lt;Xn&gt;</a><text>, #</text><a link="sa_imm_1" hover="Bitmask immediate (field &quot;N:imms:immr&quot;)">&lt;imm&gt;</a></asmtemplate>
</encoding>
<ps_section howmany="1">
<ps name="aarch64/instrs/integer/logical/immediate" mylink="aarch64.instrs.integer.logical.immediate" enclabels="" sections="1" secttype="noheading">
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer datasize = if sf == '1' then 64 else 32;
boolean setflags;
<a link="LogicalOp" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp</a> op;
case opc of
when '00' op = <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a>; setflags = FALSE;
when '01' op = <a link="LogicalOp_ORR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_ORR</a>; setflags = FALSE;
when '10' op = <a link="LogicalOp_EOR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_EOR</a>; setflags = FALSE;
when '11' op = <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a>; setflags = TRUE;
bits(datasize) imm;
if sf == '0' &amp;&amp; N != '0' then UNDEFINED;
(imm, -) = <a link="impl-aarch64.DecodeBitMasks.5" file="shared_pseudocode.xml" hover="function: (bits(M), bits(M)) DecodeBitMasks(bit immN, bits(6) imms, bits(6) immr, boolean immediate, integer M)">DecodeBitMasks</a>(N, imms, immr, TRUE, datasize);</pstext>
</ps>
</ps_section>
</iclass>
</classes>
<explanations scope="all">
<explanation enclist="EOR_32_log_imm" symboldefcount="1">
<symbol link="sa_wd_wsp">&lt;Wd|WSP&gt;</symbol>
<account encodedin="Rd">
<intro>
<para>Is the 32-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="EOR_32_log_imm" symboldefcount="1">
<symbol link="sa_wn">&lt;Wn&gt;</symbol>
<account encodedin="Rn">
<intro>
<para>Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="EOR_64_log_imm" symboldefcount="1">
<symbol link="sa_xd_sp">&lt;Xd|SP&gt;</symbol>
<account encodedin="Rd">
<intro>
<para>Is the 64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="EOR_64_log_imm" symboldefcount="1">
<symbol link="sa_xn">&lt;Xn&gt;</symbol>
<account encodedin="Rn">
<intro>
<para>Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="EOR_32_log_imm" symboldefcount="1">
<symbol link="sa_imm">&lt;imm&gt;</symbol>
<account encodedin="immr:imms">
<docvars>
<docvar key="datatype" value="32" />
</docvars>
<intro>
<para>For the 32-bit variant: is the bitmask immediate, encoded in "imms:immr".</para>
</intro>
</account>
</explanation>
<explanation enclist="EOR_64_log_imm" symboldefcount="2">
<symbol link="sa_imm_1">&lt;imm&gt;</symbol>
<account encodedin="N:immr:imms">
<docvars>
<docvar key="datatype" value="64" />
</docvars>
<intro>
<para>For the 64-bit variant: is the bitmask immediate, encoded in "N:imms:immr".</para>
</intro>
</account>
</explanation>
</explanations>
<ps_section howmany="1">
<ps name="aarch64/instrs/integer/logical/immediate" mylink="execute" enclabels="" sections="1" secttype="Operation">
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(datasize) result;
bits(datasize) operand1 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, datasize];
bits(datasize) operand2 = imm;
case op of
when <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a> result = operand1 AND operand2;
when <a link="LogicalOp_ORR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_ORR</a> result = operand1 OR operand2;
when <a link="LogicalOp_EOR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_EOR</a> result = operand1 EOR operand2;
if setflags then
PSTATE.&lt;N,Z,C,V&gt; = result&lt;datasize-1&gt;:<a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result):'00';
if d == 31 &amp;&amp; !setflags then
<a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(result, 64);
else
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, datasize] = result;</pstext>
</ps>
</ps_section>
</instructionsection>