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https://github.com/pound-emu/ballistic.git
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298 lines
18 KiB
XML
298 lines
18 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="FCVTZU_float_fix" title="FCVTZU (scalar, fixed-point) -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="float" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCVTZU" />
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</docvars>
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<heading>FCVTZU (scalar, fixed-point)</heading>
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<desc>
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<brief>
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<para>Floating-point Convert to Unsigned fixed-point, rounding toward Zero (scalar)</para>
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</brief>
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<authored>
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<para>Floating-point Convert to Unsigned fixed-point, rounding toward Zero (scalar). This instruction converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit fixed-point unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.</para>
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<para>A floating-point exception can be generated by this instruction. Depending on the settings in <xref linkend="AArch64.fpcr">FPCR</xref>, the exception results in either a flag being set in <xref linkend="AArch64.fpsr">FPSR</xref>, or a synchronous exception being generated. For more information, see <xref linkend="BEIJDDAG">Floating-point exception traps</xref>.</para>
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<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.</para>
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</authored>
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<affected_by_sme output="general-purpose register" />
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Floating-point" oneof="1" id="iclass_float" no_encodings="6" isa="A64">
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<docvars>
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<docvar key="instr-class" value="float" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCVTZU" />
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</docvars>
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<iclassintro count="6"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/float/convert/fix" tworows="1">
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<box hibit="31" name="sf" usename="1">
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<c></c>
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</box>
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<box hibit="30" settings="1">
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<c>0</c>
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</box>
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<box hibit="29" name="S" settings="1">
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<c>0</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" width="2" name="ftype" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="21" settings="1">
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<c>0</c>
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</box>
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<box hibit="20" width="2" name="rmode" usename="1" settings="2" psbits="xx">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="18" width="3" name="opcode" usename="1" settings="3" psbits="xxx">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="15" width="6" name="scale" usename="1">
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<c colspan="6"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="FCVTZU_32H_float2fix" oneofinclass="6" oneof="6" label="Half-precision to 32-bit" bitdiffs="sf == 0 && ftype == 11">
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<docvars>
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<docvar key="convert-type" value="half-to-fix32" />
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<docvar key="instr-class" value="float" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCVTZU" />
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</docvars>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
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</arch_variants>
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<box hibit="31" width="1" name="sf">
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<c>0</c>
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</box>
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<box hibit="23" width="2" name="ftype">
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate><text>FCVTZU </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_hn" hover="16-bit SIMD&FP source register (field "Rn")"><Hn></a><text>, #</text><a link="sa_fbits" hover="Number of bits after the binary point in the fixed-point destination [1-32] (field scale)"><fbits></a></asmtemplate>
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</encoding>
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<encoding name="FCVTZU_64H_float2fix" oneofinclass="6" oneof="6" label="Half-precision to 64-bit" bitdiffs="sf == 1 && ftype == 11">
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<docvars>
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<docvar key="convert-type" value="half-to-fix64" />
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<docvar key="instr-class" value="float" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCVTZU" />
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</docvars>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
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</arch_variants>
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<box hibit="31" width="1" name="sf">
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<c>1</c>
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</box>
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<box hibit="23" width="2" name="ftype">
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate><text>FCVTZU </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_hn" hover="16-bit SIMD&FP source register (field "Rn")"><Hn></a><text>, #</text><a link="sa_fbits_1" hover="Number of bits after the binary point in the fixed-point destination [1-64] (field scale)"><fbits></a></asmtemplate>
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</encoding>
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<encoding name="FCVTZU_32S_float2fix" oneofinclass="6" oneof="6" label="Single-precision to 32-bit" bitdiffs="sf == 0 && ftype == 00">
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<docvars>
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<docvar key="convert-type" value="single-to-fix32" />
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<docvar key="instr-class" value="float" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCVTZU" />
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</docvars>
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<box hibit="31" width="1" name="sf">
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<c>0</c>
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</box>
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<box hibit="23" width="2" name="ftype">
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<c>0</c>
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<c>0</c>
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</box>
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<asmtemplate><text>FCVTZU </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_sn" hover="32-bit SIMD&FP source register (field "Rn")"><Sn></a><text>, #</text><a link="sa_fbits" hover="Number of bits after the binary point in the fixed-point destination [1-32] (field scale)"><fbits></a></asmtemplate>
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</encoding>
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<encoding name="FCVTZU_64S_float2fix" oneofinclass="6" oneof="6" label="Single-precision to 64-bit" bitdiffs="sf == 1 && ftype == 00">
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<docvars>
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<docvar key="convert-type" value="single-to-fix64" />
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<docvar key="instr-class" value="float" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCVTZU" />
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</docvars>
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<box hibit="31" width="1" name="sf">
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<c>1</c>
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</box>
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<box hibit="23" width="2" name="ftype">
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<c>0</c>
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<c>0</c>
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</box>
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<asmtemplate><text>FCVTZU </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_sn" hover="32-bit SIMD&FP source register (field "Rn")"><Sn></a><text>, #</text><a link="sa_fbits_1" hover="Number of bits after the binary point in the fixed-point destination [1-64] (field scale)"><fbits></a></asmtemplate>
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</encoding>
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<encoding name="FCVTZU_32D_float2fix" oneofinclass="6" oneof="6" label="Double-precision to 32-bit" bitdiffs="sf == 0 && ftype == 01">
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<docvars>
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<docvar key="convert-type" value="double-to-fix32" />
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<docvar key="instr-class" value="float" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCVTZU" />
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</docvars>
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<box hibit="31" width="1" name="sf">
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<c>0</c>
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</box>
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<box hibit="23" width="2" name="ftype">
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate><text>FCVTZU </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_dn" hover="64-bit SIMD&FP source register (field "Rn")"><Dn></a><text>, #</text><a link="sa_fbits" hover="Number of bits after the binary point in the fixed-point destination [1-32] (field scale)"><fbits></a></asmtemplate>
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</encoding>
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<encoding name="FCVTZU_64D_float2fix" oneofinclass="6" oneof="6" label="Double-precision to 64-bit" bitdiffs="sf == 1 && ftype == 01">
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<docvars>
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<docvar key="convert-type" value="double-to-fix64" />
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<docvar key="instr-class" value="float" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCVTZU" />
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</docvars>
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<box hibit="31" width="1" name="sf">
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<c>1</c>
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</box>
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<box hibit="23" width="2" name="ftype">
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate><text>FCVTZU </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_dn" hover="64-bit SIMD&FP source register (field "Rn")"><Dn></a><text>, #</text><a link="sa_fbits_1" hover="Number of bits after the binary point in the fixed-point destination [1-64] (field scale)"><fbits></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/float/convert/fix" mylink="aarch64.instrs.float.convert.fix" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer intsize = if sf == '1' then 64 else 32;
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integer fltsize;
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<a link="FPConvOp" file="shared_pseudocode.xml" hover="enumeration FPConvOp {FPConvOp_CVT_FtoI, FPConvOp_CVT_ItoF, FPConvOp_MOV_FtoI, FPConvOp_MOV_ItoF , FPConvOp_CVT_FtoI_JS }">FPConvOp</a> op;
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<a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding;
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boolean unsigned;
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case ftype of
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when '00' fltsize = 32;
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when '01' fltsize = 64;
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when '10' UNDEFINED;
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when '11'
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if <a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then
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fltsize = 16;
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else
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UNDEFINED;
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if sf == '0' && scale<5> == '0' then UNDEFINED;
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integer fracbits = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(scale);
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case opcode<2:1>:rmode of
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when '00 11' // FCVTZ
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rounding = <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>;
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unsigned = (opcode<0> == '1');
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op = <a link="FPConvOp_CVT_FtoI" file="shared_pseudocode.xml" hover="enumeration FPConvOp {FPConvOp_CVT_FtoI, FPConvOp_CVT_ItoF, FPConvOp_MOV_FtoI, FPConvOp_MOV_ItoF , FPConvOp_CVT_FtoI_JS }">FPConvOp_CVT_FtoI</a>;
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when '01 00' // [US]CVTF
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rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR[]);
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unsigned = (opcode<0> == '1');
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op = <a link="FPConvOp_CVT_ItoF" file="shared_pseudocode.xml" hover="enumeration FPConvOp {FPConvOp_CVT_FtoI, FPConvOp_CVT_ItoF, FPConvOp_MOV_FtoI, FPConvOp_MOV_ItoF , FPConvOp_CVT_FtoI_JS }">FPConvOp_CVT_ItoF</a>;
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otherwise
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UNDEFINED;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="FCVTZU_32D_float2fix, FCVTZU_32H_float2fix, FCVTZU_32S_float2fix" symboldefcount="1">
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<symbol link="sa_wd"><Wd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FCVTZU_64D_float2fix, FCVTZU_64H_float2fix, FCVTZU_64S_float2fix" symboldefcount="1">
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<symbol link="sa_xd"><Xd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FCVTZU_32S_float2fix, FCVTZU_64S_float2fix" symboldefcount="1">
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<symbol link="sa_sn"><Sn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FCVTZU_32H_float2fix, FCVTZU_64H_float2fix" symboldefcount="1">
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<symbol link="sa_hn"><Hn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FCVTZU_32D_float2fix, FCVTZU_64D_float2fix" symboldefcount="1">
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<symbol link="sa_dn"><Dn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FCVTZU_32D_float2fix, FCVTZU_32H_float2fix, FCVTZU_32S_float2fix" symboldefcount="1">
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<symbol link="sa_fbits"><fbits></symbol>
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<account encodedin="scale">
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<intro>
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<para>For the double-precision to 32-bit, half-precision to 32-bit and single-precision to 32-bit variant: is the number of bits after the binary point in the fixed-point destination, in the range 1 to 32, encoded as 64 minus "scale".</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FCVTZU_64D_float2fix, FCVTZU_64H_float2fix, FCVTZU_64S_float2fix" symboldefcount="2">
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<symbol link="sa_fbits_1"><fbits></symbol>
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<account encodedin="scale">
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<intro>
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<para>For the double-precision to 64-bit, half-precision to 64-bit and single-precision to 64-bit variant: is the number of bits after the binary point in the fixed-point destination, in the range 1 to 64, encoded as 64 minus "scale".</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/float/convert/fix" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPEnabled64()">CheckFPEnabled64</a>();
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<a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = FPCR[];
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boolean merge = <a link="impl-shared.IsMerging.1" file="shared_pseudocode.xml" hover="function: boolean IsMerging(FPCRType fpcr)">IsMerging</a>(fpcr);
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integer fsize = if op == <a link="FPConvOp_CVT_ItoF" file="shared_pseudocode.xml" hover="enumeration FPConvOp {FPConvOp_CVT_FtoI, FPConvOp_CVT_ItoF, FPConvOp_MOV_FtoI, FPConvOp_MOV_ItoF , FPConvOp_CVT_FtoI_JS }">FPConvOp_CVT_ItoF</a> && merge then 128 else fltsize;
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bits(fsize) fltval;
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bits(intsize) intval;
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case op of
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when <a link="FPConvOp_CVT_FtoI" file="shared_pseudocode.xml" hover="enumeration FPConvOp {FPConvOp_CVT_FtoI, FPConvOp_CVT_ItoF, FPConvOp_MOV_FtoI, FPConvOp_MOV_ItoF , FPConvOp_CVT_FtoI_JS }">FPConvOp_CVT_FtoI</a>
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fltval = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, fsize];
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intval = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(fltval, fracbits, unsigned, fpcr, rounding, intsize);
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<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, intsize] = intval;
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when <a link="FPConvOp_CVT_ItoF" file="shared_pseudocode.xml" hover="enumeration FPConvOp {FPConvOp_CVT_FtoI, FPConvOp_CVT_ItoF, FPConvOp_MOV_FtoI, FPConvOp_MOV_ItoF , FPConvOp_CVT_FtoI_JS }">FPConvOp_CVT_ItoF</a>
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intval = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, intsize];
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fltval = if merge then <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[d, fsize] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(fsize);
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[fltval, 0, fltsize] = <a link="impl-shared.FixedToFP.6" file="shared_pseudocode.xml" hover="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer N)">FixedToFP</a>(intval, fracbits, unsigned, fpcr, rounding, fltsize);
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<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, fsize] = fltval;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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