mirror of
https://github.com/pound-emu/ballistic.git
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179 lines
10 KiB
XML
179 lines
10 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="FRINT64X_float" title="FRINT64X (scalar) -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="float" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FRINT64X" />
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</docvars>
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<heading>FRINT64X (scalar)</heading>
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<desc>
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<brief>
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<para>Floating-point Round to 64-bit Integer, using current rounding mode (scalar)</para>
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</brief>
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<authored>
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<para>Floating-point Round to 64-bit Integer, using current rounding mode (scalar). This instruction rounds a floating-point value in the SIMD&FP source register to an integral floating-point value that fits into a 64-bit integer size using the rounding mode that is determined by the <xref linkend="AArch64.fpcr">FPCR</xref>, and writes the result to the SIMD&FP destination register.</para>
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<para>A zero input returns a zero result with the same sign. When the result value is not numerically equal to the input value, an Inexact exception is raised. When the input is infinite, NaN or out-of-range, the instruction returns {for the corresponding result value} the most negative integer representable in the destination size, and an Invalid Operation floating-point exception is raised.</para>
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<para>A floating-point exception can be generated by this instruction. Depending on the settings in <xref linkend="AArch64.fpcr">FPCR</xref>, the exception results in either a flag being set in <xref linkend="AArch64.fpsr">FPSR</xref>, or a synchronous exception being generated. For more information, see <xref linkend="BEIJDDAG">Floating-point exception traps</xref>.</para>
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<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Floating-point" oneof="1" id="iclass_float" no_encodings="2" isa="A64">
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<docvars>
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<docvar key="instr-class" value="float" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FRINT64X" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.5" feature="FEAT_FRINTTS" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/float/arithmetic/round/frint_32_64" tworows="1">
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<box hibit="31" name="M" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" settings="1">
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<c>0</c>
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</box>
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<box hibit="29" name="S" settings="1">
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<c>0</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" width="2" name="ftype" usename="1" settings="1" psbits="xx">
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<c>0</c>
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<c>x</c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="4" settings="4">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="16" width="2" name="op" usename="1" settings="2" psbits="xx">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="14" width="5" settings="5">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="FRINT64X_S_floatdp1" oneofinclass="2" oneof="2" label="Single-precision" bitdiffs="ftype == 00">
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<docvars>
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<docvar key="datatype" value="single" />
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<docvar key="instr-class" value="float" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FRINT64X" />
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</docvars>
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<box hibit="23" width="2" name="ftype">
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<c></c>
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<c>0</c>
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</box>
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<asmtemplate><text>FRINT64X </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Rd")"><Sd></a><text>, </text><a link="sa_sn" hover="32-bit SIMD&FP source register (field "Rn")"><Sn></a></asmtemplate>
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</encoding>
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<encoding name="FRINT64X_D_floatdp1" oneofinclass="2" oneof="2" label="Double-precision" bitdiffs="ftype == 01">
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<docvars>
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<docvar key="datatype" value="double" />
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<docvar key="instr-class" value="float" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FRINT64X" />
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</docvars>
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<box hibit="23" width="2" name="ftype">
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<c></c>
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<c>1</c>
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</box>
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<asmtemplate><text>FRINT64X </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "Rd")"><Dd></a><text>, </text><a link="sa_dn" hover="64-bit SIMD&FP source register (field "Rn")"><Dn></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/float/arithmetic/round/frint_32_64" mylink="aarch64.instrs.float.arithmetic.round.frint_32_64" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFrintExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveFrintExt()">HaveFrintExt</a>() then UNDEFINED;
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer esize;
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case ftype of
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when '00' esize = 32;
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when '01' esize = 64;
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when '1x' UNDEFINED;
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integer intsize = if op<1> == '0' then 32 else 64;
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<a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = if op<0> == '0' then <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a> else <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPCR[]);</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="FRINT64X_D_floatdp1" symboldefcount="1">
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<symbol link="sa_dd"><Dd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FRINT64X_D_floatdp1" symboldefcount="1">
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<symbol link="sa_dn"><Dn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FRINT64X_S_floatdp1" symboldefcount="1">
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<symbol link="sa_sd"><Sd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FRINT64X_S_floatdp1" symboldefcount="1">
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<symbol link="sa_sn"><Sn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/float/arithmetic/round/frint_32_64" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPEnabled64()">CheckFPEnabled64</a>();
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<a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = FPCR[];
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boolean merge = <a link="impl-shared.IsMerging.1" file="shared_pseudocode.xml" hover="function: boolean IsMerging(FPCRType fpcr)">IsMerging</a>(fpcr);
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bits(128) result = if merge then <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[d, 128] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(128);
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bits(esize) operand = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, esize];
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 0, esize] = <a link="impl-shared.FPRoundIntN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundIntN(bits(N) op, FPCRType fpcr, FPRounding rounding, integer intsize)">FPRoundIntN</a>(operand, fpcr, rounding, intsize);
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<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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