mirror of
https://github.com/pound-emu/ballistic.git
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154 lines
8.9 KiB
XML
154 lines
8.9 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="GCSSTTR" title="GCSSTTR -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="GCSSTTR" />
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</docvars>
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<heading>GCSSTTR</heading>
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<desc>
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<brief>
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<para>Guarded Control Stack unprivileged Store</para>
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</brief>
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<authored>
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<para>Guarded Control Stack unprivileged Store stores a doubleword from a register to memory. The address that is used for the store is calculated from a base register.</para>
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<para>Memory accesses made by the instruction behave as if the instruction was executed at EL0 if the <xref linkend="CBAICCHA">Effective value</xref> of PSTATE.UAO is 0 and either:</para>
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<list type="unordered">
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<listitem><content>The instruction is executed at EL1 and <xref linkend="AArch64.hcr_el2">HCR_EL2</xref>.{NV, NV1} is not {1, 1}.</content></listitem>
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<listitem><content>The instruction is executed at EL2 when the <xref linkend="CBAICCHA">Effective value</xref> of <xref linkend="AArch64.hcr_el2">HCR_EL2</xref>.{E2H, TGE} is {1, 1}.</content></listitem>
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</list>
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<para>Otherwise, the memory access operates with the restrictions determined by the Exception level at which the instruction is executed.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Integer" oneof="1" id="iclass_general" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="GCSSTTR" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="FEAT_GCS" feature="FEAT_GCS" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/memory/gcs/general/register" tworows="1">
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<box hibit="31" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="26" name="V" settings="1">
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<c>0</c>
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</box>
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<box hibit="25" width="11" settings="11">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="14" width="3" name="opc" usename="1" settings="3" psbits="xxx">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="GCSSTTR_64_ldst_gcs" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="GCSSTTR" />
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</docvars>
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<asmtemplate><text>GCSSTTR </text><a link="sa_xt" hover="64-bit general-purpose register to be transferred (field "Rt")"><Xt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/gcs/general/register" mylink="aarch64.instrs.memory.gcs.general.register" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveGCS.0" file="shared_pseudocode.xml" hover="function: boolean HaveGCS()">HaveGCS</a>() then UNDEFINED;
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bits(2) effective_el;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
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boolean is_gcssttr = (opc == '001');
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if is_gcssttr then
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boolean privileged;
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case PSTATE.EL of
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when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> privileged = FALSE;
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when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> privileged = <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() && <a link="impl-shared.HaveNVExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveNVExt()">HaveNVExt</a>() && HCR_EL2.<NV,NV1> == '11';
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when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> privileged = !(<a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>() && HCR_EL2.<E2H,TGE> == '11');
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when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> privileged = TRUE;
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if <a link="impl-shared.HaveUAOExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveUAOExt()">HaveUAOExt</a>() && PSTATE.UAO == '1' then
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privileged = PSTATE.EL != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;
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if privileged then
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effective_el = PSTATE.EL;
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else
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effective_el = <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;
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else
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effective_el = PSTATE.EL;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="GCSSTTR_64_ldst_gcs" symboldefcount="1">
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<symbol link="sa_xt"><Xt></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="GCSSTTR_64_ldst_gcs" symboldefcount="1">
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<symbol link="sa_xn_sp"><Xn|SP></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/gcs/general/register" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(64) address;
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bits(64) data;
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if effective_el == PSTATE.EL then
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<a link="impl-aarch64.CheckGCSSTRTrap.0" file="shared_pseudocode.xml" hover="function: CheckGCSSTRTrap()">CheckGCSSTRTrap</a>();
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<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescGCS.2" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescGCS(bits(2) el, MemOp memop)">CreateAccDescGCS</a>(effective_el, <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>);
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if n == 31 then
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<a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
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address = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
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else
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address = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
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data = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[t, 64];
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Mem[address, 8, accdesc] = data;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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