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137 lines
6.6 KiB
XML
137 lines
6.6 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="orr_z_zz" title="ORR (vectors, unpredicated)" type="instruction">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ORR" />
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</docvars>
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<heading>ORR (vectors, unpredicated)</heading>
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<desc>
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<brief>Bitwise inclusive OR vectors (unpredicated)</brief>
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<description>
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<para>Bitwise inclusive OR all elements of the second source vector with corresponding elements of the first source vector and place the first in the corresponding elements of the destination vector. This instruction is unpredicated.</para>
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</description>
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<status>Green</status>
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<predicated>False</predicated>
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<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
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</desc>
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<alias_list howmany="1">
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<alias_list_intro>This instruction is used by the alias </alias_list_intro>
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<aliasref aliaspageid="MOV_orr_z_zz" aliasfile="mov_orr_z_zz.xml" hover="Move vector register (unpredicated)" punct=".">
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<text>MOV (vector, unpredicated)</text>
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<aliaspref>Zn == Zm</aliaspref>
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</aliasref>
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<alias_list_outro>
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<text> See </text>
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<aliastablelink />
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<text> below for details of when the alias is preferred.</text>
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</alias_list_outro>
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</alias_list>
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<classes>
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<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ORR" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="ORR-Z.ZZ-_">
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<box hibit="31" width="8" settings="8">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" name="opc<1>" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" name="opc<0>" settings="1">
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<c>1</c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Zm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="6" settings="6">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="orr_z_zz_" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="ORR" />
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</docvars>
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<asmtemplate><text>ORR </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.D, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.D, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.D</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="ORR-Z.ZZ-_" mylink="ORR-Z.ZZ-_" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="orr_z_zz_" symboldefcount="1">
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<symbol link="sa_zd"><Zd></symbol>
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<account encodedin="Zd">
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<intro>
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<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="orr_z_zz_" symboldefcount="1">
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<symbol link="sa_zn"><Zn></symbol>
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<account encodedin="Zn">
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<intro>
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<para>Is the name of the first source scalable vector register, encoded in the "Zn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="orr_z_zz_" symboldefcount="1">
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<symbol link="sa_zm"><Zm></symbol>
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<account encodedin="Zm">
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<intro>
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<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
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<ps_section howmany="1">
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<ps name="ORR-Z.ZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
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constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
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bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
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bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
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<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = operand1 OR operand2;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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