mirror of
https://github.com/pound-emu/ballistic.git
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543 lines
39 KiB
XML
543 lines
39 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="STP_fpsimd" title="STP (SIMD&FP) -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STP" />
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<docvar key="offset-type" value="off7s_s" />
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</docvars>
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<heading>STP (SIMD&FP)</heading>
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<desc>
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<brief>
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<para>Store Pair of SIMD&FP registers</para>
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</brief>
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<authored>
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<para>Store Pair of SIMD&FP registers. This instruction stores a pair of SIMD&FP registers to memory. The address used for the store is calculated from a base register value and an immediate offset.</para>
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<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
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</authored>
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</desc>
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<operationalnotes>
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<para>If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="3">
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<txt>It has encodings from 3 classes:</txt>
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<a href="#iclass_post_indexed">Post-index</a>
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<txt>, </txt>
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<a href="#iclass_pre_indexed">Pre-index</a>
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<txt> and </txt>
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<a href="#iclass_signed_scaled_offset">Signed offset</a>
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</classesintro>
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<iclass name="Post-index" oneof="3" id="iclass_post_indexed" no_encodings="3" isa="A64">
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<docvars>
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<docvar key="address-form" value="post-indexed" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STP" />
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<docvar key="offset-type" value="off7s_s" />
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</docvars>
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<iclassintro count="3"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/memory/pair/simdfp/post-idx" tworows="1">
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<box hibit="31" width="2" name="opc" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="29" width="3" settings="3">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="26" name="V" settings="1">
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<c>1</c>
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</box>
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<box hibit="25" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="22" name="L" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="21" width="7" name="imm7" usename="1">
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<c colspan="7"></c>
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</box>
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<box hibit="14" width="5" name="Rt2" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="STP_S_ldstpair_post" oneofinclass="3" oneof="9" label="32-bit" bitdiffs="opc == 00">
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<docvars>
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<docvar key="address-form" value="post-indexed" />
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<docvar key="address-form-reg-type" value="post-indexed-pair-words" />
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<docvar key="atomic-ops" value="STP-pair-words" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STP" />
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<docvar key="offset-type" value="off7s_s" />
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<docvar key="reg-type" value="pair-words" />
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</docvars>
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<box hibit="31" width="2" name="opc">
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<c>0</c>
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<c>0</c>
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</box>
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<asmtemplate><text>STP </text><a link="sa_st1" hover="First 32-bit SIMD&FP register to be transferred (field "Rt")"><St1></a><text>, </text><a link="sa_st2" hover="Second 32-bit SIMD&FP register to be transferred (field "Rt2")"><St2></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>], #</text><a link="sa_imm_5" hover="Signed immediate byte offset, multiple of 4 [-256-252] (field "imm7")"><imm></a></asmtemplate>
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</encoding>
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<encoding name="STP_D_ldstpair_post" oneofinclass="3" oneof="9" label="64-bit" bitdiffs="opc == 01">
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<docvars>
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<docvar key="address-form" value="post-indexed" />
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<docvar key="address-form-reg-type" value="post-indexed-pair-doublewords" />
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<docvar key="atomic-ops" value="STP-pair-doublewords" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STP" />
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<docvar key="offset-type" value="off7s_s" />
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<docvar key="reg-type" value="pair-doublewords" />
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</docvars>
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<box hibit="31" width="2" name="opc">
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate><text>STP </text><a link="sa_dt1" hover="First 64-bit SIMD&FP register to be transferred (field "Rt")"><Dt1></a><text>, </text><a link="sa_dt2" hover="Second 64-bit SIMD&FP register to be transferred (field "Rt2")"><Dt2></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>], #</text><a link="sa_imm_1" hover="Signed immediate byte offset, multiple of 8 [-512-504] (field "imm7")"><imm></a></asmtemplate>
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</encoding>
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<encoding name="STP_Q_ldstpair_post" oneofinclass="3" oneof="9" label="128-bit" bitdiffs="opc == 10">
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<docvars>
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<docvar key="address-form" value="post-indexed" />
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<docvar key="address-form-reg-type" value="post-indexed-pair-quadwords" />
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<docvar key="atomic-ops" value="STP-pair-quadwords" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STP" />
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<docvar key="offset-type" value="off7s_s" />
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<docvar key="reg-type" value="pair-quadwords" />
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</docvars>
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<box hibit="31" width="2" name="opc">
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<c>1</c>
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<c>0</c>
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</box>
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<asmtemplate><text>STP </text><a link="sa_qt1" hover="First 128-bit SIMD&FP register to be transferred (field "Rt")"><Qt1></a><text>, </text><a link="sa_qt2" hover="Second 128-bit SIMD&FP register to be transferred (field "Rt2")"><Qt2></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>], #</text><a link="sa_imm_3" hover="Signed immediate byte offset, multiple of 16 [-1024-1008] (field "imm7")"><imm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/pair/simdfp/post-idx" mylink="aarch64.instrs.memory.pair.simdfp.post-idx" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">boolean wback = TRUE;
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boolean postindex = TRUE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Pre-index" oneof="3" id="iclass_pre_indexed" no_encodings="3" isa="A64">
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<docvars>
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<docvar key="address-form" value="pre-indexed" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STP" />
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<docvar key="offset-type" value="off7s_s" />
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</docvars>
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<iclassintro count="3"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/memory/pair/simdfp/pre-idx" tworows="1">
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<box hibit="31" width="2" name="opc" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="29" width="3" settings="3">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="26" name="V" settings="1">
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<c>1</c>
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</box>
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<box hibit="25" width="3" settings="3">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="22" name="L" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="21" width="7" name="imm7" usename="1">
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<c colspan="7"></c>
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</box>
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<box hibit="14" width="5" name="Rt2" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="STP_S_ldstpair_pre" oneofinclass="3" oneof="9" label="32-bit" bitdiffs="opc == 00">
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<docvars>
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<docvar key="address-form" value="pre-indexed" />
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<docvar key="address-form-reg-type" value="pre-indexed-pair-words" />
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<docvar key="atomic-ops" value="STP-pair-words" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STP" />
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<docvar key="offset-type" value="off7s_s" />
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<docvar key="reg-type" value="pair-words" />
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</docvars>
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<box hibit="31" width="2" name="opc">
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<c>0</c>
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<c>0</c>
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</box>
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<asmtemplate><text>STP </text><a link="sa_st1" hover="First 32-bit SIMD&FP register to be transferred (field "Rt")"><St1></a><text>, </text><a link="sa_st2" hover="Second 32-bit SIMD&FP register to be transferred (field "Rt2")"><St2></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>, #</text><a link="sa_imm_5" hover="Signed immediate byte offset, multiple of 4 [-256-252] (field "imm7")"><imm></a><text>]!</text></asmtemplate>
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</encoding>
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<encoding name="STP_D_ldstpair_pre" oneofinclass="3" oneof="9" label="64-bit" bitdiffs="opc == 01">
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<docvars>
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<docvar key="address-form" value="pre-indexed" />
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<docvar key="address-form-reg-type" value="pre-indexed-pair-doublewords" />
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<docvar key="atomic-ops" value="STP-pair-doublewords" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STP" />
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<docvar key="offset-type" value="off7s_s" />
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<docvar key="reg-type" value="pair-doublewords" />
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</docvars>
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<box hibit="31" width="2" name="opc">
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate><text>STP </text><a link="sa_dt1" hover="First 64-bit SIMD&FP register to be transferred (field "Rt")"><Dt1></a><text>, </text><a link="sa_dt2" hover="Second 64-bit SIMD&FP register to be transferred (field "Rt2")"><Dt2></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>, #</text><a link="sa_imm_1" hover="Signed immediate byte offset, multiple of 8 [-512-504] (field "imm7")"><imm></a><text>]!</text></asmtemplate>
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</encoding>
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<encoding name="STP_Q_ldstpair_pre" oneofinclass="3" oneof="9" label="128-bit" bitdiffs="opc == 10">
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<docvars>
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<docvar key="address-form" value="pre-indexed" />
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<docvar key="address-form-reg-type" value="pre-indexed-pair-quadwords" />
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<docvar key="atomic-ops" value="STP-pair-quadwords" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STP" />
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<docvar key="offset-type" value="off7s_s" />
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<docvar key="reg-type" value="pair-quadwords" />
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</docvars>
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<box hibit="31" width="2" name="opc">
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<c>1</c>
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<c>0</c>
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</box>
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<asmtemplate><text>STP </text><a link="sa_qt1" hover="First 128-bit SIMD&FP register to be transferred (field "Rt")"><Qt1></a><text>, </text><a link="sa_qt2" hover="Second 128-bit SIMD&FP register to be transferred (field "Rt2")"><Qt2></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>, #</text><a link="sa_imm_3" hover="Signed immediate byte offset, multiple of 16 [-1024-1008] (field "imm7")"><imm></a><text>]!</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/pair/simdfp/pre-idx" mylink="aarch64.instrs.memory.pair.simdfp.pre-idx" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">boolean wback = TRUE;
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boolean postindex = FALSE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Signed offset" oneof="3" id="iclass_signed_scaled_offset" no_encodings="3" isa="A64">
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<docvars>
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<docvar key="address-form" value="signed-scaled-offset" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STP" />
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<docvar key="offset-type" value="off7s_s" />
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</docvars>
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<iclassintro count="3"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/memory/pair/simdfp/offset" tworows="1">
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<box hibit="31" width="2" name="opc" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="29" width="3" settings="3">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="26" name="V" settings="1">
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<c>1</c>
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</box>
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<box hibit="25" width="3" settings="3">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="22" name="L" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="21" width="7" name="imm7" usename="1">
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<c colspan="7"></c>
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</box>
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<box hibit="14" width="5" name="Rt2" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="STP_S_ldstpair_off" oneofinclass="3" oneof="9" label="32-bit" bitdiffs="opc == 00">
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<docvars>
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<docvar key="address-form" value="signed-scaled-offset" />
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<docvar key="address-form-reg-type" value="signed-scaled-offset-pair-words" />
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<docvar key="atomic-ops" value="STP-pair-words" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STP" />
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<docvar key="offset-type" value="off7s_s" />
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<docvar key="reg-type" value="pair-words" />
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</docvars>
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<box hibit="31" width="2" name="opc">
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<c>0</c>
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<c>0</c>
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</box>
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<asmtemplate><text>STP </text><a link="sa_st1" hover="First 32-bit SIMD&FP register to be transferred (field "Rt")"><St1></a><text>, </text><a link="sa_st2" hover="Second 32-bit SIMD&FP register to be transferred (field "Rt2")"><St2></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{</text><text>, #</text><a link="sa_imm_4" hover="Optional signed immediate byte offset, multiple of 4 [-256-252], default 0 (field "imm7")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<encoding name="STP_D_ldstpair_off" oneofinclass="3" oneof="9" label="64-bit" bitdiffs="opc == 01">
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<docvars>
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<docvar key="address-form" value="signed-scaled-offset" />
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<docvar key="address-form-reg-type" value="signed-scaled-offset-pair-doublewords" />
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<docvar key="atomic-ops" value="STP-pair-doublewords" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STP" />
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<docvar key="offset-type" value="off7s_s" />
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<docvar key="reg-type" value="pair-doublewords" />
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</docvars>
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<box hibit="31" width="2" name="opc">
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate><text>STP </text><a link="sa_dt1" hover="First 64-bit SIMD&FP register to be transferred (field "Rt")"><Dt1></a><text>, </text><a link="sa_dt2" hover="Second 64-bit SIMD&FP register to be transferred (field "Rt2")"><Dt2></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{</text><text>, #</text><a link="sa_imm" hover="Optional signed immediate byte offset, multiple of 8 [-512-504], default 0 (field "imm7")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<encoding name="STP_Q_ldstpair_off" oneofinclass="3" oneof="9" label="128-bit" bitdiffs="opc == 10">
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<docvars>
|
|
<docvar key="address-form" value="signed-scaled-offset" />
|
|
<docvar key="address-form-reg-type" value="signed-scaled-offset-pair-quadwords" />
|
|
<docvar key="atomic-ops" value="STP-pair-quadwords" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="STP" />
|
|
<docvar key="offset-type" value="off7s_s" />
|
|
<docvar key="reg-type" value="pair-quadwords" />
|
|
</docvars>
|
|
<box hibit="31" width="2" name="opc">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>STP </text><a link="sa_qt1" hover="First 128-bit SIMD&FP register to be transferred (field "Rt")"><Qt1></a><text>, </text><a link="sa_qt2" hover="Second 128-bit SIMD&FP register to be transferred (field "Rt2")"><Qt2></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{</text><text>, #</text><a link="sa_imm_2" hover="Optional signed immediate byte offset, multiple of 16 [-1024-1008], default 0 (field "imm7")"><imm></a><text>}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/memory/pair/simdfp/offset" mylink="aarch64.instrs.memory.pair.simdfp.offset" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">boolean wback = FALSE;
|
|
boolean postindex = FALSE;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="STP_D_ldstpair_off, STP_D_ldstpair_post, STP_D_ldstpair_pre" symboldefcount="1">
|
|
<symbol link="sa_dt1"><Dt1></symbol>
|
|
<account encodedin="Rt">
|
|
<intro>
|
|
<para>Is the 64-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STP_D_ldstpair_off, STP_D_ldstpair_post, STP_D_ldstpair_pre" symboldefcount="1">
|
|
<symbol link="sa_dt2"><Dt2></symbol>
|
|
<account encodedin="Rt2">
|
|
<intro>
|
|
<para>Is the 64-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STP_Q_ldstpair_off, STP_Q_ldstpair_post, STP_Q_ldstpair_pre" symboldefcount="1">
|
|
<symbol link="sa_qt1"><Qt1></symbol>
|
|
<account encodedin="Rt">
|
|
<intro>
|
|
<para>Is the 128-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STP_Q_ldstpair_off, STP_Q_ldstpair_post, STP_Q_ldstpair_pre" symboldefcount="1">
|
|
<symbol link="sa_qt2"><Qt2></symbol>
|
|
<account encodedin="Rt2">
|
|
<intro>
|
|
<para>Is the 128-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STP_S_ldstpair_off, STP_S_ldstpair_post, STP_S_ldstpair_pre" symboldefcount="1">
|
|
<symbol link="sa_st1"><St1></symbol>
|
|
<account encodedin="Rt">
|
|
<intro>
|
|
<para>Is the 32-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STP_S_ldstpair_off, STP_S_ldstpair_post, STP_S_ldstpair_pre" symboldefcount="1">
|
|
<symbol link="sa_st2"><St2></symbol>
|
|
<account encodedin="Rt2">
|
|
<intro>
|
|
<para>Is the 32-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STP_D_ldstpair_off, STP_D_ldstpair_post, STP_D_ldstpair_pre, STP_Q_ldstpair_off, STP_Q_ldstpair_post, STP_Q_ldstpair_pre, STP_S_ldstpair_off, STP_S_ldstpair_post, STP_S_ldstpair_pre" symboldefcount="1">
|
|
<symbol link="sa_xn_sp"><Xn|SP></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STP_S_ldstpair_post, STP_S_ldstpair_pre" symboldefcount="1">
|
|
<symbol link="sa_imm_5"><imm></symbol>
|
|
<account encodedin="imm7">
|
|
<docvars>
|
|
<docvar key="atomic-ops" value="STP-pair-words" />
|
|
<docvar key="reg-type" value="pair-words" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For the 32-bit post-index and 32-bit pre-index variant: is the signed immediate byte offset, a multiple of 4 in the range -256 to 252, encoded in the "imm7" field as <imm>/4.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STP_S_ldstpair_off" symboldefcount="2">
|
|
<symbol link="sa_imm_4"><imm></symbol>
|
|
<account encodedin="imm7">
|
|
<docvars>
|
|
<docvar key="address-form" value="signed-scaled-offset" />
|
|
<docvar key="address-form-reg-type" value="signed-scaled-offset-pair-words" />
|
|
<docvar key="atomic-ops" value="STP-pair-words" />
|
|
<docvar key="reg-type" value="pair-words" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For the 32-bit signed offset variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as <imm>/4.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STP_D_ldstpair_post, STP_D_ldstpair_pre" symboldefcount="3">
|
|
<symbol link="sa_imm_1"><imm></symbol>
|
|
<account encodedin="imm7">
|
|
<docvars>
|
|
<docvar key="atomic-ops" value="STP-pair-doublewords" />
|
|
<docvar key="reg-type" value="pair-doublewords" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For the 64-bit post-index and 64-bit pre-index variant: is the signed immediate byte offset, a multiple of 8 in the range -512 to 504, encoded in the "imm7" field as <imm>/8.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STP_D_ldstpair_off" symboldefcount="4">
|
|
<symbol link="sa_imm"><imm></symbol>
|
|
<account encodedin="imm7">
|
|
<docvars>
|
|
<docvar key="address-form" value="signed-scaled-offset" />
|
|
<docvar key="address-form-reg-type" value="signed-scaled-offset-pair-doublewords" />
|
|
<docvar key="atomic-ops" value="STP-pair-doublewords" />
|
|
<docvar key="reg-type" value="pair-doublewords" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For the 64-bit signed offset variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as <imm>/8.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STP_Q_ldstpair_post, STP_Q_ldstpair_pre" symboldefcount="5">
|
|
<symbol link="sa_imm_3"><imm></symbol>
|
|
<account encodedin="imm7">
|
|
<docvars>
|
|
<docvar key="atomic-ops" value="STP-pair-quadwords" />
|
|
<docvar key="reg-type" value="pair-quadwords" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For the 128-bit post-index and 128-bit pre-index variant: is the signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, encoded in the "imm7" field as <imm>/16.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STP_Q_ldstpair_off" symboldefcount="6">
|
|
<symbol link="sa_imm_2"><imm></symbol>
|
|
<account encodedin="imm7">
|
|
<docvars>
|
|
<docvar key="address-form" value="signed-scaled-offset" />
|
|
<docvar key="address-form-reg-type" value="signed-scaled-offset-pair-quadwords" />
|
|
<docvar key="atomic-ops" value="STP-pair-quadwords" />
|
|
<docvar key="reg-type" value="pair-quadwords" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For the 128-bit signed offset variant: is the optional signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, defaulting to 0 and encoded in the "imm7" field as <imm>/16.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/memory/pair/simdfp/post-idx" mylink="postdecode" enclabels="" sections="1" secttype="Shared Decode">
|
|
<pstext mayhavelinks="1" section="Postdecode" rep_section="postdecode">integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
|
integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
|
|
integer t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2);
|
|
boolean nontemporal = FALSE;
|
|
<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop = if L == '1' then <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> else <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;
|
|
if opc == '11' then UNDEFINED;
|
|
integer scale = 2 + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc);
|
|
integer datasize = 8 << scale;
|
|
bits(64) offset = <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm7, 64), scale);
|
|
boolean tagchecked = wback || n != 31;
|
|
|
|
boolean rt_unknown = FALSE;
|
|
|
|
if memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> && t == t2 then
|
|
<a link="Constraint" file="shared_pseudocode.xml" hover="enumeration Constraint { Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE, Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY, Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH, Constraint_NC, Constraint_WT, Constraint_WB, Constraint_FORCE, Constraint_FORCENOSLCHECK, Constraint_MAPTOALLOCATED, Constraint_PMSCR_PCT_VIRT }">Constraint</a> c = <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_LDPOVERLAP" file="shared_pseudocode.xml" hover="enumeration Unpredictable { Unpredictable_VMSR, Unpredictable_WBOVERLAPLD, Unpredictable_WBOVERLAPST, Unpredictable_LDPOVERLAP, Unpredictable_BASEOVERLAP, Unpredictable_DATAOVERLAP, Unpredictable_DEVPAGE2, Unpredictable_INSTRDEVICE, Unpredictable_RESCPACR, Unpredictable_RESMAIR, Unpredictable_S1CTAGGED, Unpredictable_S2RESMEMATTR, Unpredictable_RESTEXCB, Unpredictable_RESPRRR, Unpredictable_RESDACR, Unpredictable_RESVTCRS, Unpredictable_RESTnSZ, Unpredictable_RESTCF, Unpredictable_DEVICETAGSTORE, Unpredictable_OORTnSZ, Unpredictable_LARGEIPA, Unpredictable_ESRCONDPASS, Unpredictable_ILZEROIT, Unpredictable_ILZEROT, Unpredictable_BPVECTORCATCHPRI, Unpredictable_VCMATCHHALF, Unpredictable_VCMATCHDAPA, Unpredictable_WPMASKANDBAS, Unpredictable_WPBASCONTIGUOUS, Unpredictable_RESWPMASK, Unpredictable_WPMASKEDBITS, Unpredictable_RESBPWPCTRL, Unpredictable_BPNOTIMPL, Unpredictable_RESBPTYPE, Unpredictable_BPNOTCTXCMP, Unpredictable_BPMATCHHALF, Unpredictable_BPMISMATCHHALF, Unpredictable_RESTARTALIGNPC, Unpredictable_RESTARTZEROUPPERPC, Unpredictable_ZEROUPPER, Unpredictable_ERETZEROUPPERPC, Unpredictable_A32FORCEALIGNPC, Unpredictable_SMD, Unpredictable_NONFAULT, Unpredictable_SVEZEROUPPER, Unpredictable_SVELDNFDATA, Unpredictable_SVELDNFZERO, Unpredictable_CHECKSPNONEACTIVE, Unpredictable_SMEZEROUPPER, Unpredictable_NVNV1, Unpredictable_Shareability, Unpredictable_AFUPDATE, Unpredictable_DBUPDATE, Unpredictable_IESBinDebug, Unpredictable_BADPMSFCR, Unpredictable_ZEROBTYPE, Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP, Unpredictable_RESERVEDNSxB, Unpredictable_WFxTDEBUG, Unpredictable_LS64UNSUPPORTED, Unpredictable_MISALIGNEDATOMIC, Unpredictable_CLEARERRITEZERO, Unpredictable_ALUEXCEPTIONRETURN, Unpredictable_IGNORETRAPINDEBUG, Unpredictable_DBGxVR_RESS, Unpredictable_PMUEVENTCOUNTER, Unpredictable_PMSCR_PCT, Unpredictable_CounterReservedForEL2, Unpredictable_BRBFILTRATE, Unpredictable_MOPSOVERLAP31, Unpredictable_STOREONLYTAGCHECKEDCAS, Unpredictable_RESTC }">Unpredictable_LDPOVERLAP</a>);
|
|
assert c IN {<a link="Constraint_UNKNOWN" file="shared_pseudocode.xml" hover="enumeration Constraint { Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE, Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY, Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH, Constraint_NC, Constraint_WT, Constraint_WB, Constraint_FORCE, Constraint_FORCENOSLCHECK, Constraint_MAPTOALLOCATED, Constraint_PMSCR_PCT_VIRT }">Constraint_UNKNOWN</a>, <a link="Constraint_UNDEF" file="shared_pseudocode.xml" hover="enumeration Constraint { Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE, Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY, Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH, Constraint_NC, Constraint_WT, Constraint_WB, Constraint_FORCE, Constraint_FORCENOSLCHECK, Constraint_MAPTOALLOCATED, Constraint_PMSCR_PCT_VIRT }">Constraint_UNDEF</a>, <a link="Constraint_NOP" file="shared_pseudocode.xml" hover="enumeration Constraint { Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE, Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY, Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH, Constraint_NC, Constraint_WT, Constraint_WB, Constraint_FORCE, Constraint_FORCENOSLCHECK, Constraint_MAPTOALLOCATED, Constraint_PMSCR_PCT_VIRT }">Constraint_NOP</a>};
|
|
case c of
|
|
when <a link="Constraint_UNKNOWN" file="shared_pseudocode.xml" hover="enumeration Constraint { Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE, Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY, Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH, Constraint_NC, Constraint_WT, Constraint_WB, Constraint_FORCE, Constraint_FORCENOSLCHECK, Constraint_MAPTOALLOCATED, Constraint_PMSCR_PCT_VIRT }">Constraint_UNKNOWN</a> rt_unknown = TRUE; // result is UNKNOWN
|
|
when <a link="Constraint_UNDEF" file="shared_pseudocode.xml" hover="enumeration Constraint { Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE, Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY, Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH, Constraint_NC, Constraint_WT, Constraint_WB, Constraint_FORCE, Constraint_FORCENOSLCHECK, Constraint_MAPTOALLOCATED, Constraint_PMSCR_PCT_VIRT }">Constraint_UNDEF</a> UNDEFINED;
|
|
when <a link="Constraint_NOP" file="shared_pseudocode.xml" hover="enumeration Constraint { Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE, Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY, Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH, Constraint_NC, Constraint_WT, Constraint_WB, Constraint_FORCE, Constraint_FORCENOSLCHECK, Constraint_MAPTOALLOCATED, Constraint_PMSCR_PCT_VIRT }">Constraint_NOP</a> <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/memory/pair/simdfp/post-idx" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPEnabled64()">CheckFPEnabled64</a>();
|
|
bits(64) address;
|
|
bits(datasize) data1;
|
|
bits(datasize) data2;
|
|
constant integer dbytes = datasize DIV 8;
|
|
|
|
<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(memop, nontemporal, tagchecked);
|
|
|
|
if n == 31 then
|
|
<a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
|
|
address = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
|
|
else
|
|
address = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
|
|
|
|
if ! postindex then
|
|
address = address + offset;
|
|
|
|
case memop of
|
|
when <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>
|
|
data1 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[t, datasize];
|
|
data2 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[t2, datasize];
|
|
Mem[address + 0 , dbytes, accdesc] = data1;
|
|
Mem[address + dbytes, dbytes, accdesc] = data2;
|
|
|
|
when <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>
|
|
data1 = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[address + 0 , dbytes, accdesc];
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|
data2 = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[address + dbytes, dbytes, accdesc];
|
|
if rt_unknown then
|
|
data1 = bits(datasize) UNKNOWN;
|
|
data2 = bits(datasize) UNKNOWN;
|
|
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[t, datasize] = data1;
|
|
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[t2, datasize] = data2;
|
|
|
|
if wback then
|
|
if postindex then
|
|
address = address + offset;
|
|
if n == 31 then
|
|
<a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = address;
|
|
else
|
|
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[n, 64] = address;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|