mirror of
https://github.com/pound-emu/ballistic.git
synced 2026-01-31 01:15:21 +01:00
236 lines
12 KiB
XML
236 lines
12 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
|
|
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
|
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
|
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
|
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
|
|
|
<instructionsection id="FCSEL_float" title="FCSEL -- A64" type="instruction">
|
|
<docvars>
|
|
<docvar key="instr-class" value="float" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FCSEL" />
|
|
</docvars>
|
|
<heading>FCSEL</heading>
|
|
<desc>
|
|
<brief>
|
|
<para>Floating-point Conditional Select (scalar)</para>
|
|
</brief>
|
|
<authored>
|
|
<para>Floating-point Conditional Select (scalar). This instruction allows the SIMD&FP destination register to take the value from either one or the other of two SIMD&FP source registers. If the condition passes, the first SIMD&FP source register value is taken, otherwise the second SIMD&FP source register value is taken.</para>
|
|
<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
|
|
</authored>
|
|
</desc>
|
|
<operationalnotes>
|
|
<para>If PSTATE.DIT is 1:</para>
|
|
<list type="unordered">
|
|
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
|
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
|
</list>
|
|
</operationalnotes>
|
|
<alias_list howmany="0"></alias_list>
|
|
<classes>
|
|
<iclass name="Floating-point" oneof="1" id="iclass_float" no_encodings="3" isa="A64">
|
|
<docvars>
|
|
<docvar key="instr-class" value="float" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FCSEL" />
|
|
</docvars>
|
|
<iclassintro count="3"></iclassintro>
|
|
<regdiagram form="32" psname="aarch64/instrs/float/move/fp/select">
|
|
<box hibit="31" name="M" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" name="S" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="ftype" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="cond" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="FCSEL_H_floatsel" oneofinclass="3" oneof="3" label="Half-precision" bitdiffs="ftype == 11">
|
|
<docvars>
|
|
<docvar key="datatype" value="half" />
|
|
<docvar key="instr-class" value="float" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FCSEL" />
|
|
</docvars>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
|
|
</arch_variants>
|
|
<box hibit="23" width="2" name="ftype">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>FCSEL </text><a link="sa_hd" hover="16-bit SIMD&FP destination register (field "Rd")"><Hd></a><text>, </text><a link="sa_hn" hover="First 16-bit SIMD&FP source register (field "Rn")"><Hn></a><text>, </text><a link="sa_hm" hover="Second 16-bit SIMD&FP source register (field "Rm")"><Hm></a><text>, </text><a link="sa_cond" hover="Standard condition (field "cond")"><cond></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="FCSEL_S_floatsel" oneofinclass="3" oneof="3" label="Single-precision" bitdiffs="ftype == 00">
|
|
<docvars>
|
|
<docvar key="datatype" value="single" />
|
|
<docvar key="instr-class" value="float" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FCSEL" />
|
|
</docvars>
|
|
<box hibit="23" width="2" name="ftype">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>FCSEL </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Rd")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Rn")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Rm")"><Sm></a><text>, </text><a link="sa_cond" hover="Standard condition (field "cond")"><cond></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="FCSEL_D_floatsel" oneofinclass="3" oneof="3" label="Double-precision" bitdiffs="ftype == 01">
|
|
<docvars>
|
|
<docvar key="datatype" value="double" />
|
|
<docvar key="instr-class" value="float" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FCSEL" />
|
|
</docvars>
|
|
<box hibit="23" width="2" name="ftype">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>FCSEL </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "Rd")"><Dd></a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "Rn")"><Dn></a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&FP source register (field "Rm")"><Dm></a><text>, </text><a link="sa_cond" hover="Standard condition (field "cond")"><cond></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/float/move/fp/select" mylink="aarch64.instrs.float.move.fp.select" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
|
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
|
|
|
integer datasize;
|
|
case ftype of
|
|
when '00' datasize = 32;
|
|
when '01' datasize = 64;
|
|
when '10' UNDEFINED;
|
|
when '11'
|
|
if <a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then
|
|
datasize = 16;
|
|
else
|
|
UNDEFINED;
|
|
|
|
bits(4) condition = cond;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="FCSEL_D_floatsel" symboldefcount="1">
|
|
<symbol link="sa_dd"><Dd></symbol>
|
|
<account encodedin="Rd">
|
|
<intro>
|
|
<para>Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FCSEL_D_floatsel" symboldefcount="1">
|
|
<symbol link="sa_dn"><Dn></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the 64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FCSEL_D_floatsel" symboldefcount="1">
|
|
<symbol link="sa_dm"><Dm></symbol>
|
|
<account encodedin="Rm">
|
|
<intro>
|
|
<para>Is the 64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FCSEL_H_floatsel" symboldefcount="1">
|
|
<symbol link="sa_hd"><Hd></symbol>
|
|
<account encodedin="Rd">
|
|
<intro>
|
|
<para>Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FCSEL_H_floatsel" symboldefcount="1">
|
|
<symbol link="sa_hn"><Hn></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FCSEL_H_floatsel" symboldefcount="1">
|
|
<symbol link="sa_hm"><Hm></symbol>
|
|
<account encodedin="Rm">
|
|
<intro>
|
|
<para>Is the 16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FCSEL_S_floatsel" symboldefcount="1">
|
|
<symbol link="sa_sd"><Sd></symbol>
|
|
<account encodedin="Rd">
|
|
<intro>
|
|
<para>Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FCSEL_S_floatsel" symboldefcount="1">
|
|
<symbol link="sa_sn"><Sn></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the 32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FCSEL_S_floatsel" symboldefcount="1">
|
|
<symbol link="sa_sm"><Sm></symbol>
|
|
<account encodedin="Rm">
|
|
<intro>
|
|
<para>Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FCSEL_D_floatsel, FCSEL_H_floatsel, FCSEL_S_floatsel" symboldefcount="1">
|
|
<symbol link="sa_cond"><cond></symbol>
|
|
<account encodedin="cond">
|
|
<intro>
|
|
<para>Is one of the standard conditions, encoded in the "cond" field in the standard way.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/float/move/fp/select" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPEnabled64()">CheckFPEnabled64</a>();
|
|
bits(datasize) result;
|
|
|
|
result = if <a link="impl-shared.ConditionHolds.1" file="shared_pseudocode.xml" hover="function: boolean ConditionHolds(bits(4) cond)">ConditionHolds</a>(condition) then <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize] else <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, datasize];
|
|
|
|
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, datasize] = result;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|