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251 lines
11 KiB
XML
251 lines
11 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="AT_SYS" title="AT -- A64" type="alias">
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<docvars>
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<docvar key="alias_mnemonic" value="AT" />
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<docvar key="instr-class" value="system" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SYS" />
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</docvars>
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<heading>AT</heading>
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<desc>
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<brief>
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<para>Address Translate</para>
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</brief>
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<authored>
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<para>Address Translate. For more information, see <xref linkend="BABEJJJE">op0==0b01, cache maintenance, TLB maintenance, and address translation instructions</xref>.</para>
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</authored>
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</desc>
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<aliasto refiform="sys.xml" iformid="SYS">SYS</aliasto>
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<classes>
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<iclass name="System" oneof="1" id="iclass_system" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="system" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SYS" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/system/sysops" tworows="1">
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<box hibit="31" width="10" settings="10">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="21" name="L" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="20" width="2" name="op0" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="18" width="3" name="op1" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="15" width="4" name="CRn" usename="1" settings="4" psbits="xxxx">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="11" width="4" name="CRm" usename="1" settings="3" psbits="xxxx">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>x</c>
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</box>
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<box hibit="7" width="3" name="op2" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="4" width="5" name="Rt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="AT_SYS_CR_systeminstrs" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="alias_mnemonic" value="AT" />
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<docvar key="instr-class" value="system" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SYS" />
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</docvars>
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<asmtemplate><text>AT </text><a link="sa_at_op" hover="AT instruction name, as listed for AT system instruction group (field "op1:CRm<0>:op2") [S1E0R,S1E0W,S1E1R,S1E1RP (FEAT_PAN2),S1E1W,S1E1WP (FEAT_PAN2),S1E2R,S1E2W,S1E3R,S1E3W,S12E0R,S12E0W,S12E1R,S12E1W]"><at_op></a><text>, </text><a link="sa_xt_1" hover="64-bit general-purpose source register (field "Rt")"><Xt></a></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="sys.xml#SYS_CR_systeminstrs">SYS</a><text> #</text><a link="sa_op1" hover="3-bit unsigned immediate [0-7] (field "op1")"><op1></a><text>, C7, </text><a link="sa_cm" hover="Name 'Cm', with 'm' [0-15] (field "CRm")"><Cm></a><text>, #</text><a link="sa_op2" hover="3-bit unsigned immediate [0-7] (field "op2")"><op2></a><text>, </text><a link="sa_xt_1" hover="64-bit general-purpose source register (field "Rt")"><Xt></a></asmtemplate>
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<aliascond><a link="impl-aarch64.SysOp.4" file="shared_pseudocode.xml" hover="function: SystemOp SysOp(bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2)">SysOp</a>(op1,'0111',CRm,op2) == <a link="Sys_AT" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_AT</a></aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="AT_SYS_CR_systeminstrs" symboldefcount="1">
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<symbol link="sa_at_op"><at_op></symbol>
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<definition encodedin="op1:CRm<0>:op2">
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<intro>Is an AT instruction name, as listed for the AT system instruction group, </intro>
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<table class="valuetable">
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<tgroup cols="4">
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<thead>
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<row>
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<entry class="bitfield">op1</entry>
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<entry class="bitfield">CRm<0></entry>
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<entry class="bitfield">op2</entry>
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<entry class="symbol"><at_op></entry>
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<entry class="symbol">Architectural Feature</entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">000</entry>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">000</entry>
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<entry class="symbol">S1E1R</entry>
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<entry class="feature" />
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</row>
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<row>
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<entry class="bitfield">000</entry>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">001</entry>
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<entry class="symbol">S1E1W</entry>
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<entry class="feature" />
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</row>
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<row>
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<entry class="bitfield">000</entry>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">010</entry>
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<entry class="symbol">S1E0R</entry>
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<entry class="feature" />
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</row>
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<row>
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<entry class="bitfield">000</entry>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">011</entry>
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<entry class="symbol">S1E0W</entry>
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<entry class="feature" />
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</row>
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<row>
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<entry class="bitfield">000</entry>
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<entry class="bitfield">1</entry>
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<entry class="bitfield">000</entry>
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<entry class="symbol">S1E1RP</entry>
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<entry class="feature">
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<arch_variants>
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<arch_variant feature="FEAT_PAN2" />
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</arch_variants>
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</entry>
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</row>
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<row>
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<entry class="bitfield">000</entry>
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<entry class="bitfield">1</entry>
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<entry class="bitfield">001</entry>
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<entry class="symbol">S1E1WP</entry>
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<entry class="feature">
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<arch_variants>
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<arch_variant feature="FEAT_PAN2" />
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</arch_variants>
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</entry>
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</row>
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<row>
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<entry class="bitfield">100</entry>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">000</entry>
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<entry class="symbol">S1E2R</entry>
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<entry class="feature" />
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</row>
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<row>
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<entry class="bitfield">100</entry>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">001</entry>
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<entry class="symbol">S1E2W</entry>
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<entry class="feature" />
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</row>
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<row>
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<entry class="bitfield">100</entry>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">100</entry>
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<entry class="symbol">S12E1R</entry>
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<entry class="feature" />
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</row>
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<row>
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<entry class="bitfield">100</entry>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">101</entry>
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<entry class="symbol">S12E1W</entry>
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<entry class="feature" />
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</row>
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<row>
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<entry class="bitfield">100</entry>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">110</entry>
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<entry class="symbol">S12E0R</entry>
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<entry class="feature" />
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</row>
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<row>
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<entry class="bitfield">100</entry>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">111</entry>
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<entry class="symbol">S12E0W</entry>
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<entry class="feature" />
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</row>
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<row>
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<entry class="bitfield">110</entry>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">000</entry>
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<entry class="symbol">S1E3R</entry>
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<entry class="feature" />
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</row>
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<row>
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<entry class="bitfield">110</entry>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">001</entry>
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<entry class="symbol">S1E3W</entry>
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<entry class="feature" />
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="AT_SYS_CR_systeminstrs" symboldefcount="1">
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<symbol link="sa_op1"><op1></symbol>
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<account encodedin="op1">
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<intro>
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<para>Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op1" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="AT_SYS_CR_systeminstrs" symboldefcount="1">
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<symbol link="sa_cm"><Cm></symbol>
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<account encodedin="CRm">
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<intro>
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<para>Is a name 'Cm', with 'm' in the range 0 to 15, encoded in the "CRm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="AT_SYS_CR_systeminstrs" symboldefcount="1">
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<symbol link="sa_op2"><op2></symbol>
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<account encodedin="op2">
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<intro>
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<para>Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="AT_SYS_CR_systeminstrs" symboldefcount="1">
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<symbol link="sa_xt_1"><Xt></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the 64-bit name of the general-purpose source register, encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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</instructionsection>
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