mirror of
https://github.com/pound-emu/ballistic.git
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157 lines
7.6 KiB
XML
157 lines
7.6 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="BIC_and_z_zi" title="BIC (immediate)" type="alias">
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<docvars>
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<docvar key="alias_mnemonic" value="BIC" />
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="AND" />
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</docvars>
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<heading>BIC (immediate)</heading>
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<desc>
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<brief>Bitwise clear bits using immediate (unpredicated)</brief>
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<description>
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<para>Bitwise clear bits using immediate with each 64-bit element of the source vector, and destructively place the results in the corresponding elements of the source vector. The immediate is a 64-bit value consisting of a single run of ones or zeros repeating every 2, 4, 8, 16, 32 or 64 bits. This instruction is unpredicated.</para>
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</description>
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<status>Green</status>
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<predicated>False</predicated>
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<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
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<takes_movprfx>True</takes_movprfx>
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</desc>
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<aliasto refiform="and_z_zi.xml" iformid="and_z_zi">AND (immediate)</aliasto>
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<classes>
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<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="AND" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="AND-Z.ZI-_">
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<box hibit="31" width="8" settings="8">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="23" name="opc<1>" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="opc" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" width="4" settings="4">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="17" width="13" name="imm13" usename="1">
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<c colspan="13"></c>
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</box>
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<box hibit="4" width="5" name="Zdn" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="BIC_and_z_zi_" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="alias_mnemonic" value="BIC" />
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="AND" />
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</docvars>
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<asmtemplate><text>BIC </text><a link="sa_zdn" hover="Source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "imm13<12>:imm13<5:0>") [B,D,H,S]"><T></a><text>, </text><a link="sa_zdn" hover="Source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "imm13<12>:imm13<5:0>") [B,D,H,S]"><T></a><text>, #</text><a link="sa_const" hover="64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits (field "imm13")"><const></a></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="and_z_zi.xml#and_z_zi_">AND</a><text> </text><a link="sa_zdn" hover="Source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "imm13<12>:imm13<5:0>") [B,D,H,S]"><T></a><text>, </text><a link="sa_zdn" hover="Source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "imm13<12>:imm13<5:0>") [B,D,H,S]"><T></a><text>, #(-</text><a link="sa_const" hover="64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits (field "imm13")"><const></a><text> - 1)</text></asmtemplate>
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<aliascond>Never</aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="BIC_and_z_zi_" symboldefcount="1">
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<symbol link="sa_zdn"><Zdn></symbol>
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<account encodedin="Zdn">
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<intro>
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<para>Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="BIC_and_z_zi_" symboldefcount="1">
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<symbol link="sa_t"><T></symbol>
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<definition encodedin="imm13<12>:imm13<5:0>">
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<intro>Is the size specifier, </intro>
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<table class="valuetable">
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<tgroup cols="3">
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<thead>
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<row>
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<entry class="bitfield">imm13<12></entry>
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<entry class="bitfield">imm13<5:0></entry>
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<entry class="symbol"><T></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">0xxxxx</entry>
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<entry class="symbol">S</entry>
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</row>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">10xxxx</entry>
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<entry class="symbol">H</entry>
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</row>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">110xxx</entry>
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<entry class="symbol">B</entry>
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</row>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">1110xx</entry>
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<entry class="symbol">B</entry>
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</row>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">11110x</entry>
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<entry class="symbol">B</entry>
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</row>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">111110</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">111111</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="bitfield">xxxxxx</entry>
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<entry class="symbol">D</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="BIC_and_z_zi_" symboldefcount="1">
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<symbol link="sa_const"><const></symbol>
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<account encodedin="imm13">
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<intro>
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<para>Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits, encoded in the "imm13" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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</instructionsection>
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