mirror of
https://github.com/pound-emu/ballistic.git
synced 2026-01-31 01:15:21 +01:00
409 lines
20 KiB
XML
409 lines
20 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
|
|
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
|
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
|
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
|
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
|
|
|
<instructionsection id="FCVTZS_advsimd_fix" title="FCVTZS (vector, fixed-point) -- A64" type="instruction">
|
|
<docvars>
|
|
<docvar key="instr-class" value="advsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FCVTZS" />
|
|
</docvars>
|
|
<heading>FCVTZS (vector, fixed-point)</heading>
|
|
<desc>
|
|
<brief>
|
|
<para>Floating-point Convert to Signed fixed-point, rounding toward Zero (vector)</para>
|
|
</brief>
|
|
<authored>
|
|
<para>Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.</para>
|
|
<para>A floating-point exception can be generated by this instruction. Depending on the settings in <xref linkend="AArch64.fpcr">FPCR</xref>, the exception results in either a flag being set in <xref linkend="AArch64.fpsr">FPSR</xref>, or a synchronous exception being generated. For more information, see <xref linkend="BEIJDDAG">Floating-point exception traps</xref>.</para>
|
|
<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.</para>
|
|
</authored>
|
|
</desc>
|
|
<alias_list howmany="0"></alias_list>
|
|
<classes>
|
|
<classesintro count="2">
|
|
<txt>It has encodings from 2 classes:</txt>
|
|
<a href="#iclass_sisd">Scalar</a>
|
|
<txt> and </txt>
|
|
<a href="#iclass_simd">Vector</a>
|
|
</classesintro>
|
|
<iclass name="Scalar" oneof="2" id="iclass_sisd" no_encodings="1" isa="A64">
|
|
<docvars>
|
|
<docvar key="advsimd-type" value="sisd" />
|
|
<docvar key="instr-class" value="advsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FCVTZS" />
|
|
</docvars>
|
|
<iclassintro count="1"></iclassintro>
|
|
<regdiagram form="32" psname="aarch64/instrs/vector/shift/conv/float/sisd" tworows="1">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" name="U" usename="1" settings="1" psbits="x">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="28" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="immh" usename="1" settings="4" constraint="!= 0000" psbits="xxxx">
|
|
<c colspan="4">!= 0000</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="immb" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="5" name="opcode" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="FCVTZS_asisdshf_C" oneofinclass="1" oneof="2" label="">
|
|
<docvars>
|
|
<docvar key="advsimd-type" value="sisd" />
|
|
<docvar key="instr-class" value="advsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FCVTZS" />
|
|
</docvars>
|
|
<asmtemplate><text>FCVTZS </text><a link="sa_v" hover="Width specifier (field "immh") [D,H,S]"><V></a><a link="sa_d" hover="SIMD&FP destination register number (field "Rd")"><d></a><text>, </text><a link="sa_v" hover="Width specifier (field "immh") [D,H,S]"><V></a><a link="sa_n" hover="First SIMD&FP source register number (field "Rn")"><n></a><text>, #</text><a link="sa_fbits_1" hover="Number of fractional bits [1-the operand width] (field "immh:immb") [(32-Uint(immh:immb)),(64-UInt(immh:immb)),(128-UInt(immh:immb))]"><fbits></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/vector/shift/conv/float/sisd" mylink="aarch64.instrs.vector.shift.conv.float.sisd" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
|
|
|
if immh IN {'000x'} || (immh IN {'001x'} && !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;
|
|
integer esize = if immh IN {'1xxx'} then 64 else if immh IN {'01xx'} then 32 else 16;
|
|
integer datasize = esize;
|
|
integer elements = 1;
|
|
|
|
integer fracbits = (esize * 2) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(immh:immb);
|
|
boolean unsigned = (U == '1');
|
|
<a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="Vector" oneof="2" id="iclass_simd" no_encodings="1" isa="A64">
|
|
<docvars>
|
|
<docvar key="advsimd-type" value="simd" />
|
|
<docvar key="instr-class" value="advsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FCVTZS" />
|
|
</docvars>
|
|
<iclassintro count="1"></iclassintro>
|
|
<regdiagram form="32" psname="aarch64/instrs/vector/shift/conv/float/simd" tworows="1">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="U" usename="1" settings="1" psbits="x">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="28" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="immh" usename="1" settings="4" constraint="!= 0000">
|
|
<c colspan="4">!= 0000</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="immb" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="5" name="opcode" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="FCVTZS_asimdshf_C" oneofinclass="1" oneof="2" label="">
|
|
<docvars>
|
|
<docvar key="advsimd-type" value="simd" />
|
|
<docvar key="instr-class" value="advsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FCVTZS" />
|
|
</docvars>
|
|
<asmtemplate><text>FCVTZS </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "immh:Q") [2D,2S,4H,4S,8H,SEE(asimdimm)]"><T></a><text>, </text><a link="sa_vn" hover="SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "immh:Q") [2D,2S,4H,4S,8H,SEE(asimdimm)]"><T></a><text>, #</text><a link="sa_fbits" hover="Number of fractional bits [1-the element width] (field "immh:immb") [(32-Uint(immh:immb)),(64-UInt(immh:immb)),(128-UInt(immh:immb)),SEE(asimdimm)]"><fbits></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/vector/shift/conv/float/simd" mylink="aarch64.instrs.vector.shift.conv.float.simd" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
|
|
|
if immh == '0000' then <a link="asimdimm" file="encodingindex.xml" hover="handled by an instruction in the 'Advanced SIMD modified immediate' class">SEE(asimdimm)</a>;
|
|
if immh IN {'000x'} || (immh IN {'001x'} && !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;
|
|
if immh<3>:Q == '10' then UNDEFINED;
|
|
integer esize = if immh IN {'1xxx'} then 64 else if immh IN {'01xx'} then 32 else 16;
|
|
integer datasize = if Q == '1' then 128 else 64;
|
|
integer elements = datasize DIV esize;
|
|
|
|
integer fracbits = (esize * 2) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(immh:immb);
|
|
boolean unsigned = (U == '1');
|
|
<a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="FCVTZS_asisdshf_C" symboldefcount="1">
|
|
<symbol link="sa_v"><V></symbol>
|
|
<definition encodedin="immh">
|
|
<intro>Is a width specifier, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">immh</entry>
|
|
<entry class="symbol"><V></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">000x</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">001x</entry>
|
|
<entry class="symbol">H</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01xx</entry>
|
|
<entry class="symbol">S</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1xxx</entry>
|
|
<entry class="symbol">D</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.2-A" />
|
|
</arch_variants>
|
|
</explanation>
|
|
<explanation enclist="FCVTZS_asisdshf_C" symboldefcount="1">
|
|
<symbol link="sa_d"><d></symbol>
|
|
<account encodedin="Rd">
|
|
<intro>
|
|
<para>Is the number of the SIMD&FP destination register, in the "Rd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FCVTZS_asisdshf_C" symboldefcount="1">
|
|
<symbol link="sa_n"><n></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the number of the first SIMD&FP source register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FCVTZS_asimdshf_C" symboldefcount="1">
|
|
<symbol link="sa_vd"><Vd></symbol>
|
|
<account encodedin="Rd">
|
|
<intro>
|
|
<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FCVTZS_asimdshf_C" symboldefcount="1">
|
|
<symbol link="sa_t"><T></symbol>
|
|
<definition encodedin="immh:Q">
|
|
<intro>Is an arrangement specifier, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">immh</entry>
|
|
<entry class="bitfield">Q</entry>
|
|
<entry class="symbol"><T></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0000</entry>
|
|
<entry class="bitfield">x</entry>
|
|
<entry class="symbol" iclasslink="asimdimm" iclasslinkfile="encodingindex.xml">SEE Advanced SIMD modified immediate</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0001</entry>
|
|
<entry class="bitfield">x</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">001x</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">4H</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">001x</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">8H</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01xx</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">2S</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01xx</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">4S</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1xxx</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1xxx</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">2D</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.2-A" />
|
|
</arch_variants>
|
|
</explanation>
|
|
<explanation enclist="FCVTZS_asimdshf_C" symboldefcount="1">
|
|
<symbol link="sa_vn"><Vn></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the name of the SIMD&FP source register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FCVTZS_asisdshf_C" symboldefcount="1">
|
|
<symbol link="sa_fbits_1"><fbits></symbol>
|
|
<definition encodedin="immh:immb">
|
|
<intro>For the scalar variant: is the number of fractional bits, in the range 1 to the operand width, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">immh</entry>
|
|
<entry class="symbol"><fbits></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">000x</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">001x</entry>
|
|
<entry class="symbol">(32-Uint(immh:immb))</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01xx</entry>
|
|
<entry class="symbol">(64-UInt(immh:immb))</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1xxx</entry>
|
|
<entry class="symbol">(128-UInt(immh:immb))</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.2-A" />
|
|
</arch_variants>
|
|
</explanation>
|
|
<explanation enclist="FCVTZS_asimdshf_C" symboldefcount="2">
|
|
<symbol link="sa_fbits"><fbits></symbol>
|
|
<definition encodedin="immh:immb">
|
|
<intro>For the vector variant: is the number of fractional bits, in the range 1 to the element width, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">immh</entry>
|
|
<entry class="symbol"><fbits></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0000</entry>
|
|
<entry class="symbol" iclasslink="asimdimm" iclasslinkfile="encodingindex.xml">SEE Advanced SIMD modified immediate</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0001</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">001x</entry>
|
|
<entry class="symbol">(32-Uint(immh:immb))</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01xx</entry>
|
|
<entry class="symbol">(64-UInt(immh:immb))</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1xxx</entry>
|
|
<entry class="symbol">(128-UInt(immh:immb))</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.2-A" />
|
|
</arch_variants>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/vector/shift/conv/float/sisd" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
|
|
bits(datasize) operand = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
|
|
|
|
bits(esize) element;
|
|
<a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = FPCR[];
|
|
boolean merge = elements == 1 && <a link="impl-shared.IsMerging.1" file="shared_pseudocode.xml" hover="function: boolean IsMerging(FPCRType fpcr)">IsMerging</a>(fpcr);
|
|
bits(128) result = if merge then <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[d, 128] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(128);
|
|
for e = 0 to elements-1
|
|
element = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
|
|
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(element, fracbits, unsigned, fpcr, rounding, esize);
|
|
|
|
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|