mirror of
https://github.com/pound-emu/ballistic.git
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327 lines
17 KiB
XML
327 lines
17 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="FMLAL_advsimd_elt" title="FMLAL, FMLAL2 (by element) -- A64" type="instruction">
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<docvars>
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<docvar key="advsimd-reguse" value="2reg-element" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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</docvars>
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<heading>FMLAL, FMLAL2 (by element)</heading>
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<desc>
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<brief>
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<para>Floating-point fused Multiply-Add Long to accumulator (by element)</para>
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</brief>
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<authored>
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<para>Floating-point fused Multiply-Add Long to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the product to the corresponding vector element of the destination SIMD&FP register. The instruction does not round the result of the multiply before the accumulation.</para>
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<para>A floating-point exception can be generated by this instruction. Depending on the settings in <xref linkend="AArch64.fpcr">FPCR</xref>, the exception results in either a flag being set in <xref linkend="AArch64.fpsr">FPSR</xref>, or a synchronous exception being generated. For more information, see <xref linkend="BEIJDDAG">Floating-point exception traps</xref>.</para>
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<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
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<para>In Armv8.2 and Armv8.3, this is an <arm-defined-word>optional</arm-defined-word> instruction. From Armv8.4 it is mandatory for all implementations to support it.</para>
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<note>
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<para><xref linkend="AArch64.id_aa64isar0_el1">ID_AA64ISAR0_EL1</xref>.FHM indicates whether this instruction is supported.</para>
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</note>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from 2 classes:</txt>
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<a href="#iclass_fmlal">FMLAL</a>
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<txt> and </txt>
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<a href="#iclass_fmlal2">FMLAL2</a>
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</classesintro>
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<iclass name="FMLAL" oneof="2" id="iclass_fmlal" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-reguse" value="2reg-element" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FMLAL" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FHM" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/binary/element/mul-acc/mul_norounding_i/lower" tworows="1">
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<box hibit="31" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="29" name="U" settings="1">
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<c>0</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="23" name="size[1]" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="sz" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="21" name="L" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="19" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" name="opcode[3]" settings="1">
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<c>0</c>
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</box>
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<box hibit="14" name="S" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="13" width="2" name="opcode[1:0]" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="11" name="H" usename="1">
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<c></c>
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</box>
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<box hibit="10" settings="1">
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="FMLAL_asimdelem_LH" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="advsimd-reguse" value="2reg-element" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FMLAL" />
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</docvars>
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<asmtemplate><text>FMLAL </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_ta" hover="Arrangement specifier (field "Q") [2S,4S]"><Ta></a><text>, </text><a link="sa_vn" hover="First SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_tb" hover="Arrangement specifier (field "Q") [2H,4H]"><Tb></a><text>, </text><a link="sa_vm" hover="Second SIMD&FP source register (field "Rm")"><Vm></a><text>.H[</text><a link="sa_index" hover="Element index (field "H:L:M")"><index></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/arithmetic/binary/element/mul-acc/mul_norounding_i/lower" mylink="aarch64.instrs.vector.arithmetic.binary.element.mul-acc.mul_norounding_i.lower" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFP16MulNoRoundingToFP32Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16MulNoRoundingToFP32Ext()">HaveFP16MulNoRoundingToFP32Ext</a>() then UNDEFINED;
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Rm); // Vm can only be in bottom 16 registers.
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if sz == '1' then UNDEFINED;
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integer index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(H:L:M);
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integer esize = 32;
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integer datasize = if Q=='1' then 128 else 64;
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integer elements = datasize DIV esize;
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boolean sub_op = (S == '1');
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integer part = 0;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="FMLAL2" oneof="2" id="iclass_fmlal2" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-reguse" value="2reg-element" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FMLAL2" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FHM" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/binary/element/mul-acc/mul_norounding_i/upper" tworows="1">
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<box hibit="31" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="29" name="U" settings="1">
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<c>1</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="23" name="size[1]" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="sz" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="21" name="L" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="19" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" name="opcode[3]" settings="1">
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<c>1</c>
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</box>
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<box hibit="14" name="S" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="13" width="2" name="opcode[1:0]" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="11" name="H" usename="1">
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<c></c>
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</box>
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<box hibit="10" settings="1">
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="FMLAL2_asimdelem_LH" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="advsimd-reguse" value="2reg-element" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FMLAL2" />
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</docvars>
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<asmtemplate><text>FMLAL2 </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_ta" hover="Arrangement specifier (field "Q") [2S,4S]"><Ta></a><text>, </text><a link="sa_vn" hover="First SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_tb" hover="Arrangement specifier (field "Q") [2H,4H]"><Tb></a><text>, </text><a link="sa_vm" hover="Second SIMD&FP source register (field "Rm")"><Vm></a><text>.H[</text><a link="sa_index" hover="Element index (field "H:L:M")"><index></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/arithmetic/binary/element/mul-acc/mul_norounding_i/upper" mylink="aarch64.instrs.vector.arithmetic.binary.element.mul-acc.mul_norounding_i.upper" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFP16MulNoRoundingToFP32Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16MulNoRoundingToFP32Ext()">HaveFP16MulNoRoundingToFP32Ext</a>() then UNDEFINED;
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Rm); // Vm can only be in bottom 16 registers.
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if sz == '1' then UNDEFINED;
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integer index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(H:L:M);
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integer esize = 32;
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integer datasize = if Q=='1' then 128 else 64;
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integer elements = datasize DIV esize;
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boolean sub_op = (S == '1');
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integer part = 1;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="FMLAL_asimdelem_LH, FMLAL2_asimdelem_LH" symboldefcount="1">
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<symbol link="sa_vd"><Vd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FMLAL_asimdelem_LH, FMLAL2_asimdelem_LH" symboldefcount="1">
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<symbol link="sa_ta"><Ta></symbol>
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<definition encodedin="Q">
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<intro>Is an arrangement specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">Q</entry>
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<entry class="symbol"><Ta></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">2S</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">4S</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="FMLAL_asimdelem_LH, FMLAL2_asimdelem_LH" symboldefcount="1">
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<symbol link="sa_vn"><Vn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the name of the first SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FMLAL_asimdelem_LH, FMLAL2_asimdelem_LH" symboldefcount="1">
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<symbol link="sa_tb"><Tb></symbol>
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<definition encodedin="Q">
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<intro>Is an arrangement specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">Q</entry>
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<entry class="symbol"><Tb></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">2H</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">4H</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="FMLAL_asimdelem_LH, FMLAL2_asimdelem_LH" symboldefcount="1">
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<symbol link="sa_vm"><Vm></symbol>
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<account encodedin="Rm">
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<intro>
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<para>Is the name of the second SIMD&FP source register, encoded in the "Rm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FMLAL_asimdelem_LH, FMLAL2_asimdelem_LH" symboldefcount="1">
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<symbol link="sa_index"><index></symbol>
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<account encodedin="H:L:M">
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<intro>
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<para>Is the element index, encoded in the "H:L:M" fields.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/arithmetic/binary/element/mul-acc/mul_norounding_i/lower" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
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bits(datasize DIV 2) operand1 = <a link="impl-aarch64.Vpart.read.3" file="shared_pseudocode.xml" hover="accessor: bits(width) Vpart[integer n, integer part, integer width]">Vpart</a>[n,part,datasize DIV 2];
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bits(128) operand2 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, 128];
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bits(datasize) operand3 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[d, datasize];
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bits(datasize) result;
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bits(esize DIV 2) element1;
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bits(esize DIV 2) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize DIV 2];
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for e = 0 to elements-1
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element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize DIV 2];
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if sub_op then element1 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.FPMulAddH.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAddH(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, FPCRType fpcr)">FPMulAddH</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2, FPCR[]);
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<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, datasize] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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