mirror of
https://github.com/pound-emu/ballistic.git
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264 lines
12 KiB
XML
264 lines
12 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="FRECPX_advsimd" title="FRECPX -- A64" type="instruction">
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<docvars>
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<docvar key="advsimd-type" value="sisd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FRECPX" />
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</docvars>
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<heading>FRECPX</heading>
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<desc>
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<brief>
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<para>Floating-point Reciprocal exponent (scalar)</para>
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</brief>
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<authored>
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<para>Floating-point Reciprocal exponent (scalar). This instruction finds an approximate reciprocal exponent for the source SIMD&FP register and writes the result to the destination SIMD&FP register.</para>
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<para>This instruction can generate a floating-point exception. Depending on the settings in <xref linkend="AArch64.fpcr">FPCR</xref>, the exception results in either a flag being set in <xref linkend="AArch64.fpsr">FPSR</xref> or a synchronous exception being generated. For more information, see <xref linkend="BEIJDDAG">Floating-point exception traps</xref>.</para>
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<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from 2 classes:</txt>
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<a href="#iclass_half">Half-precision</a>
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<txt> and </txt>
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<a href="#iclass_single_and_double">Single-precision and double-precision</a>
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</classesintro>
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<iclass name="Half-precision" oneof="2" id="iclass_half" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-datatype" value="sisd-half" />
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<docvar key="advsimd-type" value="sisd" />
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<docvar key="datatype" value="half" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FRECPX" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/unary/special/frecpx-fp16">
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<box hibit="31" width="2" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="29" name="U" settings="1">
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<c>0</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" name="a" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" width="6" settings="6">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="16" width="5" name="opcode" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="FRECPX_asisdmiscfp16_R" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="advsimd-datatype" value="sisd-half" />
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<docvar key="advsimd-type" value="sisd" />
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<docvar key="datatype" value="half" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FRECPX" />
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</docvars>
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<asmtemplate><text>FRECPX </text><a link="sa_hd" hover="16-bit SIMD&FP destination register (field "Rd")"><Hd></a><text>, </text><a link="sa_hn" hover="16-bit SIMD&FP source register (field "Rn")"><Hn></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/arithmetic/unary/special/frecpx-fp16" mylink="aarch64.instrs.vector.arithmetic.unary.special.frecpx-fp16" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer esize = 16;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Single-precision and double-precision" oneof="2" id="iclass_single_and_double" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-datatype" value="sisd-single-and-double" />
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<docvar key="advsimd-type" value="sisd" />
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<docvar key="datatype" value="single-and-double" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FRECPX" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/unary/special/frecpx">
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<box hibit="31" width="2" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="29" name="U" settings="1">
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<c>0</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" name="size[1]" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="sz" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="5" settings="5">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="16" width="5" name="opcode" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="FRECPX_asisdmisc_R" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="advsimd-datatype" value="sisd-single-and-double" />
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<docvar key="advsimd-type" value="sisd" />
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<docvar key="datatype" value="single-and-double" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FRECPX" />
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</docvars>
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<asmtemplate><text>FRECPX </text><a link="sa_v" hover="Width specifier (field "sz") [D,S]"><V></a><a link="sa_d" hover="SIMD&FP destination register number (field "Rd")"><d></a><text>, </text><a link="sa_v" hover="Width specifier (field "sz") [D,S]"><V></a><a link="sa_n" hover="SIMD&FP source register number (field "Rn")"><n></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/arithmetic/unary/special/frecpx" mylink="aarch64.instrs.vector.arithmetic.unary.special.frecpx" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer esize = 32 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="FRECPX_asisdmiscfp16_R" symboldefcount="1">
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<symbol link="sa_hd"><Hd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FRECPX_asisdmiscfp16_R" symboldefcount="1">
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<symbol link="sa_hn"><Hn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FRECPX_asisdmisc_R" symboldefcount="1">
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<symbol link="sa_v"><V></symbol>
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<definition encodedin="sz">
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<intro>Is a width specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">sz</entry>
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<entry class="symbol"><V></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">S</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">D</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="FRECPX_asisdmisc_R" symboldefcount="1">
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<symbol link="sa_d"><d></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the number of the SIMD&FP destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FRECPX_asisdmisc_R" symboldefcount="1">
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<symbol link="sa_n"><n></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the number of the SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/arithmetic/unary/special/frecpx-fp16" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPEnabled64()">CheckFPEnabled64</a>();
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bits(esize) operand = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, esize];
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<a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = FPCR[];
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boolean merge = <a link="impl-shared.IsMerging.1" file="shared_pseudocode.xml" hover="function: boolean IsMerging(FPCRType fpcr)">IsMerging</a>(fpcr);
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bits(128) result = if merge then <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[d, 128] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(128);
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 0, esize] = <a link="impl-shared.FPRecpX.2" file="shared_pseudocode.xml" hover="function: bits(N) FPRecpX(bits(N) op, FPCRType fpcr_in)">FPRecpX</a>(operand, fpcr);
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<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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